TAS5162DDVR datasheet(3/29 Pages) TI

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MODE Selection Pins for Both Packages

Package Heat Dissipation Ratings

(1)

TAS5162

SLES194C – OCTOBER 2006 – REVISED MAY 2007

GENERAL INFORMATION (continued)

MODE PINS

PWM INPUT

OUTPUT CONFIGURATION

PROTECTION SCHEME

2N (1) AD/BD modulation

2 channels BTL output

BTL mode, full protection (2)

2N (1) AD/BD modulation

2 channels BTL output

BTL mode, latching shutdown (2)

1N (1) AD modulation

2 channels BTL output

BTL mode, full protection (2)

1N (1) AD modulation

1 channel PBTL output

PBTL mode, full protection. Only PWM_A input

is used.

Protection works similarly to BTL mode (2). Only

difference in SE mode is that OUT_X is Hi-Z

1N (1) AD modulation

4 channels SE output

instead of a pulldown through internal pulldown

resistor.

Protection works similarly to SE Mode (2)

4 channels SE output - No

(1,0,0); however, the PWM input protection is

1N (1) AD modulation

PWM Input protection, latching

disabled. Also, overcurrent detection will latch if

shutdown

an error occurs.

Reserved

(1)

The 1N and 2N naming convention is used to indicate the required number of PWM lines to the power stage per channel in a specific

mode.

(2)

An overload protection (OLP) occurring on A or B causes both channels to shut down. An OLP on C or D works similarly. Global errors

like overtemperature error (OTE), undervoltage protection (UVP), and power-on reset (POR) affect all channels.

PARAMETER

TAS5162DKD

TAS5162DDV

RθJC (°C/W)—2 BTL or 4 SE channels (8 transistors)

1.0

1.1

RθJC (°C/W)—1 BTL or 2 SE channel(s) (4 transistors)

1.5

2.2

RθJC (°C/W)—(1 transistor)

5.0

7.4

Pad area(2)

80 mm2

34 mm2

(1)

JC is junction-to-case, CH is case-to-heatsink.

(2)

RθCH is an important consideration. Assume a 2-mil thickness of typical thermal grease between the pad area and the heatsink and both

channels active. The RθCH with this condition is 2.6°C/W for the DKD package and 4.0°C/W for the DDV package.

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