Philips Semiconductors

Product specification

PCK2510SA

50–150 MHz 1:10 SDRAM clock driver

2000 Dec 01

6

TIMING REQUIREMENTS

Over recommended ranges of supply voltage and operating free-air temperature

SYMBOL

PARAMETER

MIN

MAX

UNIT

Clock frequency

50

150

MHz

Input clock duty cycle

40

60

%

1

ms

NOTE:

1. Time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal. For phase lock to be obtained,

a fixed-frequency, fixed-phase reference signal must be present at CLK. Until phase lock is obtained, the specifications for propagation

delay, skew, and jitter parameters given in the switching characteristics table are not applicable.

SWITCHING CHARACTERISTICS

PARAMETER

FROM

TO

UNIT

PARAMETER

(INPUT)/CONDITION

(OUTPUT)

MIN

TYP

MAX

UNIT

t

2

CLKIN

↑ = 100 MHz to 133 MHz

FBIN

↑

–100

100

ps

CLKIN

↑ = 66 MHz

FBIN

↑

–125

125

ps

CLKIN

↑ = 100 MHz to 133 MHz

FBIN

↑

–50

50

ps

Any Y or FBOUT

Any Y or FBOUT

200

ps

CLKIN = 100 MHz to 133 MHz

Any Y or FBOUT

–80

80

ps

CLKIN = 100 MHz to 133 MHz

Any Y or FBOUT

|65|

ps

Duty cycle

F(CLKIN

> 60 MHz)

Any Y or FBOUT

47

53

%

Any Y or FBOUT

2.5

1

V/ns

Any Y or FBOUT

2.5

1

V/ns

NOTES:

1. These parameters are not production tested.

2. This is considered as static phase offset.