Philips Semiconductors

Product specification

PCK2510SA

50–150 MHz 1:10 SDRAM clock driver

2000 Dec 01

4

FUNCTIONAL BLOCK DIAGRAM

SW00383

FBOUT

FBIN

CLK

G

11

24

13

23

PLL

1Y9

1Y8

1Y7

1Y6

1Y5

1Y4

1Y3

1Y2

1Y1

1Y0

3

4

5

8

9

15

16

17

20

21

12

The PLL clock distribution device and A[L]VC registered drivers reduce

signal loads on the memory controller and prevent timing delays and

waveform distortions that would cause unreliable operation.

A[L]VC

PCK2510SA

A[L]VC

FRONT SIDE

A[L]VC

SW00440