AT90USB646 datasheet(35/435 Pages) ATMEL

35 / 435 page

7593D–AVR–07/06

AT90USB64/128

• Bit 3..2 – SRW11, SRW10: Wait-state Select Bits for Upper Sector

The SRW11 and SRW10 bits control the number of wait-states for the upper sector of the exter-

nal memory address space, see Table 5-5.

• Bit 1..0 – SRW01, SRW00: Wait-state Select Bits for Lower Sector

The SRW01 and SRW00 bits control the number of wait-states for the lower sector of the exter-

nal memory address space, see Table 5-5.

Note:

1. n = 0 or 1 (lower/upper sector).

For further details of the timing and wait-states of the External Memory Interface, see Figures

5-6 through Figures 5-9 for how the setting of the SRW bits affects the timing.

5.5.7

External Memory Control Register B – XMCRB

• Bit 7– XMBK: External Memory Bus-keeper Enable

Writing XMBK to one enables the bus keeper on the AD7:0 lines. When the bus keeper is

enabled, AD7:0 will keep the last driven value on the lines even if the XMEM interface has tri-

stated the lines. Writing XMBK to zero disables the bus keeper. XMBK is not qualified with SRE,

Table 5-4.

Sector limits with different settings of SRL2..0

SRL2

SRL1

SRL0

Sector Limits

Lower sector = N/A

Upper sector = 0x2100 - 0xFFFF

Lower sector = 0x2100 - 0x3FFF

Upper sector = 0x4000 - 0xFFFF

Lower sector = 0x2100 - 0x5FFF

Upper sector = 0x6000 - 0xFFFF

Lower sector = 0x2100 - 0x7FFF

Upper sector = 0x8000 - 0xFFFF

Lower sector = 0x2100 - 0x9FFF

Upper sector = 0xA000 - 0xFFFF

Lower sector = 0x2100 - 0xBFFF

Upper sector = 0xC000 - 0xFFFF

Lower sector = 0x2100 - 0xDFFF

Upper sector = 0xE000 - 0xFFFF

Table 5-5.

Wait States

(1)

SRWn1

SRWn0

Wait States

No wait-states

Wait one cycle during read/write strobe

Wait two cycles during read/write strobe

Wait two cycles during read/write and wait one cycle before driving out

new address

Bit

7654

210

XMBK

–

XMM2

XMM1

XMM0

XMCRB

Read/Write

R/W

Initial Value

0000

000

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