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ST10F276 датащи(PDF) 224 Page - STMicroelectronics

номер детали ST10F276
подробное описание детали  16-bit MCU with MAC unit, 832 Kbyte Flash memory and 68 Kbyte RAM
PDF  229 Pages
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производитель  STMICROELECTRONICS [STMicroelectronics]
домашняя страница  http://www.st.com
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ST10F276 датащи(HTML) 224 Page - STMicroelectronics

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Electrical characteristics
ST10F276
224/229
Slave mode
VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF
Table 109.
Slave mode
Symbol
Parameter
Max. baud rate
6.6 MBd(1)
@FCPU = 40 MHz
(<SSCBR> = 0002h)
1.
Maximum baud rate is in reality 8Mbaud, that can be reached with 64 MHz CPU clock and <SSCBR> set to
‘3h’, or with 48 MHz CPU clock and <SSCBR> set to ‘2h’. When 40 MHz CPU clock is used the maximum
baud rate cannot be higher than 6.6Mbaud (<SSCBR> = ‘2h’) due to the limited granularity of <SSCBR>.
Value ‘1h’ for <SSCBR> may be used only with CPU clock lower than 32 MHz (after checking that timings
are in line with the target master).
Variable baud rate
(<SSCBR> = 0001h -
FFFFh)
Unit
Min.
Max.
Min.
Max.
t310
SR
SSC clock cycle time (2)
2.
Formula for SSC Clock Cycle time:
t310 = 4 TCL * (<SSCBR> + 1)
Where <SSCBR> represents the content of the SSC baud rate register, taken as unsigned 16-bit integer.
Minimum limit allowed for t310 is 125ns (corresponding to 8Mbaud).
150
150
8TCL
262144 TCL
ns
t311
SR
SSC clock high time
63
–
t310 / 2 – 12
–
t312
SR
SSC clock low time
t313
SR
SSC clock rise time
–
10
–
10
t314
SR
SSC clock fall time
t315
CC
Write data valid after shift
edge
55
2TCL + 30
t316
CC
Write data hold after shift
edge
0
–
0
–
t317p SR
Read data setup time before
latch edge, phase error
detection on (SSCPEN = 1)
62
4TCL + 12
t318p SR
Read data hold time after
latch edge, phase error
detection on (SSCPEN = 1)
87
6TCL + 12
t317
SR
Read data setup time before
latch edge, phase error
detection off (SSCPEN = 0)
66
t318
SR
Read data hold time after
latch edge, phase error
detection off (SSCPEN = 0)
31
2TCL + 6



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