 |
поискавой системы для электроныых деталей |
|
|
поискавой системы для электроныых деталей |
|
ST10F276 датащи(PDF) 220 Page - STMicroelectronics |
|
|
|||||||||||||||||||||||||||||
ST10F276 датащи(HTML) 220 Page - STMicroelectronics |
|
|
220 / 229 page  Electrical characteristics ST10F276 220/229 23.8.21 External bus arbitration VDD = 5V ±10%, VSS = 0V, TA = -40 to +125°C, CL = 50pF Figure 66. External bus arbitration (releasing the bus) 1. The ST10F276 will complete the currently running bus cycle before granting bus access. 2. This is the first possibility for BREQ to become active. 3. The CS outputs will be resistive high (pull-up) after t64. Table 107. External bus arbitration Symbol Parameter FCPU = 40 MHz TCL = 12.5ns Variable CPU Clock 1/2 TCL = 1 to 64 MHz Min. Max. Min. Max. t61 SR HOLD input setup time to CLKOUT 18.5 – 18.5 – ns t62 CC CLKOUT to HLDA high or BREQ low delay – 12.5 – 12.5 t63 CC CLKOUT to HLDA low or BREQ high delay t64 CC CSx release 1 20 20 t65 CC CSx drive – 4 15 – 4 15 t66 CC Other signals release 1 –20 – 20 t67 CC Other signals drive – 4 15 – 4 15 t61 t63 t66 (1) t64 1) 2) t62 3) CLKOUT HOLD HLDA BREQ Others CSx (P6.x) |
|
ссылки URL |
| Вашему бизинису помогли Аллдатащит? [ DONATE ] |
Что такое Аллдатащит | реклама | контакт | Конфиденциальность | Ссылка на техническое описание | обмен ссыками | поиск по производителю All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
Russian ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
