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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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ST10F276 датащи(PDF) 212 Page - STMicroelectronics |
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ST10F276 датащи(HTML) 212 Page - STMicroelectronics |
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212 / 229 page  Electrical characteristics ST10F276 212/229 23.8.19 Demultiplexed bus VDD = 5V ±10%, VSS = 0V, TA = –40 to +125°C, CL = 50pF, ALE cycle time = 4 TCL + 2tA + tC + tF (50ns at 40 MHz CPU clock without wait states). Table 105. Demultiplexed bus Symbol Parameter FCPU = 40 MHz TCL = 12.5ns Variable CPU clock 1/2 TCL = 1 to 64 MHz Min. Max. Min. Max. t5 CC ALE high time 4 + t A – TCL – 8.5 + t A – ns t6 CC Address setup to ALE 1.5 + t A – TCL – 11 + t A – ns t80 CC Address/Unlatched CS setup to RD, WR (with RW-delay) 12.5 + 2t A – 2TCL – 12.5 + 2t A – ns t81 CC Address/Unlatched CS setup to RD, WR (no RW-delay) 0.5 + 2t A – TCL – 12 + 2t A – ns t12 CC RD, WR low time (with RW-delay) 15.5 + t C – 2TCL – 9.5 + t C – ns t13 CC RD, WR low time (no RW-delay) 28 + t C – 3TCL – 9.5 + t C – ns t14 SR RD to valid data in (with RW-delay) –6 + t C – 2TCL – 19 + t C ns t15 SR RD to valid data in (no RW-delay) – 18.5 + t C – 3TCL – 19 + t C ns t16 SR ALE low to valid data in – 17.5 + t A + tC – 3TCL – 20 + t A + tC ns t17 SR Address/Unlatched CS to valid data in – 20 + 2 t A + tC – 4TCL – 30 + 2 t A + t C ns t18 SR Data hold after RD rising edge 0– 0 – ns t20 SR Data float after RD rising edge (with RW-delay)3(1) – 16.5 + t F – 2TCL – 8.5 + t F + 2 t A ns t21 SR Data float after RD rising edge (no RW- delay) 1 –4 + t F – TCL – 8.5 + t F + 2tA ns t22 CC Data valid to WR 10 + t C – 2TCL – 15 + t C – ns t24 CC Data hold after WR 4 + t F – TCL – 8.5 + t F – ns t26 CC ALE rising edge after RD, WR –10 + t F – –10 + t F – ns t28 CC Address/Unlatched CS hold after RD, WR (2) 0 + t F –0 + t F – ns t28h CC Address/Unlatched CS hold after WRH – 5 + t F – – 5 + t F – ns |
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