ST10F276 datasheet(193/229 Pages) STMICROELECTRONICS

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ST10F276

Electrical characteristics

193/229

23.7.6

Example of external network sizing

The following hypothesis is formulated in order to proceed with designing the external net-

work on A/D converter input pins:

–

Analog signal source bandwidth (f0):

10 kHz

–

Conversion rate (fC):

25 kHz

–

Sampling time (TS):

µs

–

Pin input capacitance (CP1):

5pF

–

Pin input routing capacitance (CP2):

1pF

–

Sampling capacitance (CS):

4pF

–

Maximum input current injection (IINJ):

3mA

–

Maximum analog source voltage (VAM): 12V

–

Analog source impedance (RS):

100

Ω

–

Channel switch resistance (RSW):

500

Ω

–

Sampling switch resistance (RAD):

200

Ω

Supposing to design the filter with the pole exactly at the maximum frequency of the

signal, the time constant of the filter is:

Using the relation between CF and CS and taking some margin (4000 instead of 2048),

it is possible to define CF:

As a consequence of Step 1 and 2, RC can be chosen:

Considering the current injection limitation and supposing that the source can go up to

12V, the total series resistance can be defined as:

from which is now simple to define the value of RL:

Now, the three elements of the external circuit RF, CF and RL are defined. Some conditions

discussed in the previous paragraphs have been used to size the component; the others

must now be verified. The relation which allows to minimize the accuracy error introduced by

the switched capacitance equivalent resistance is in this case:

So the error due to the voltage partitioning between the real resistive path and CS is less

RCCF

πf0

------------

15.9

µs

CF 4000CS

⋅

16nF

πf

0CF

--------------------

995

Ω 1kΩ

≅

RS RF RL

VAM

IINJ

-------------

Ω

VAM

IINJ

------------- RF RS 2.9kΩ

–

REQ

fCCS

---------------

10M

Ω

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