PCD5096 datasheet(26/52 Pages) PHILIPS

26 / 52 page

1997 Jan 22

Philips Semiconductors

Preliminary speciﬁcation

Universal codec

PCD5096

10 I2C-BUS INTERFACE

The PCD5096 is programmed by writing to the control

registers (CR0 to CR6) and loading the SDR using the

I2C-bus interface. The master on the I2C-bus is either a

PCD509x DECT processor or an external microcontroller.

The memory map of the PCD5096 is given in Chapter 8.

It consists of 128 words (16 bits wide) of system data

IOM buffers, IOM control data and DSP parameters) and

7 words (16 bits wide) of control registers mapped at

addresses 78H to 7EH.

The I2C-bus interface uses word and byte access to the

RAM and to the control registers. For byte access the

address is not incremented automatically. For word

access the address is incremented after two data bytes

(low, high byte) in order to be able to fill the memory

without a full I2C-bus protocol (start, slave address, stop

bits).

The protocol is shown in Figs 12 to 15. I2C_BYTE = 1, for

byte access and I2C_BYTE = 0, for word access.

I2C_BSEL = 1 for selecting the high byte and

I2C_BSEL = 0 for selecting the low byte. For control

registers with less than 8 bits, there is no difference

between word access, high byte access and low byte

access.

The PCD5096 has two pins (A1 and A0) for programming

the slave address. This means that a maximum of four

devices can be located on a board without glue logic.

The I2C-bus slave address allocated for the PCD5096 is

shown in Fig.11.

Fig.11 PCD5096 I2C-bus slave address.

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