PCD5002A datasheet(3/48 Pages) PHILIPS

3 / 48 page

1999 Jan 08

Philips Semiconductors

Product speciﬁcation

Enhanced Pager Decoder for

APOC1/POCSAG

PCD5002A

FEATURES

• Wide operating supply voltage range: 1.5 to 6.0 V

• EEPROM programming requires only 2.0 V supply

• Low operating current: 50 µA typ. (ON), 25 µA typ.

(OFF)

• Temperature range −25 to +70 °C

• “CCIR radio paging Code No. 1” (POCSAG) compatible

• Supports Advanced Pager Operator’s Code Phase 1

(APOC1) for extended battery economy

• 512, 1200 and 2400 bits/s data rates using 76.8 kHz

crystal

• Built-in data filter (16 times oversampling) and bit clock

recovery

• Advanced ACCESS® synchronization algorithm

• 2-bit random and (optional) 4-bit burst error correction

• Up to 6 user addresses Receiver Identity Codes (RICs),

each with 4 functions/alert cadences

• Optional automatic call termination when bit error rate is

high

• Up to 6 user address frames, independently

programmable

• Standard POCSAG sync word, plus up to 4 user

programmable sync words

• Continuous data decoding upon reception of user

programmable sync word (optional)

• Received data inversion (optional)

• Call alert via beeper, vibrator or LED

• 2-level acoustic alert using single external transistor

• Alert control: automatic (POCSAG type), via cadence

• Separate power control of receiver and RF oscillator for

battery economy

• Dedicated pin for easy control of superheterodyne

receiver

• Synthesizer set-up and control interface (3-line serial)

• On-chip EEPROM for storage of user addresses (RICs),

pager configuration and synthesizer data

• On-chip SRAM buffer for message data

• Slave I2C-bus interface to microcontroller for transfer of

message data, status/control and EEPROM

programming (data transfer at up to 100 kbits/s)

• Wake-up interrupt for microcontroller, programmable

polarity

• Direct and I2C-bus control of operating status (ON/OFF)

• Battery-low indication (external detector)

• Out-of-range condition indication

• Real-time clock reference output

• On-chip voltage doubler

• Interfaces directly to UAA2080 and UAA2082 paging

receivers.

APPLICATIONS

• Advanced display pagers (POCSAG and APOC1)

• Basic alert-only pagers

• Information services

• Personal organizers

• Telepoint

• Telemetry/data transmission.

GENERAL DESCRIPTION

The PCD5002A is a very low power pager decoder and

controller, capable of handling both standard POCSAG

and the advanced APOC1 code. Continuous data

decoding upon reception of a dedicated sync word is

available for news pager applications.

Data rates supported are 512, 1200 and 2400 bits/s using

a single 76.8 kHz crystal. On-chip EEPROM is

programmable using a minimum supply voltage of 2.0 V,

allowing ‘over-the-air’ programming. I2C-bus compatible.

ORDERING INFORMATION

TYPE NUMBER

PACKAGE

NAME

DESCRIPTION

VERSION

PCD5002AH

LQFP32 plastic low proﬁle quad ﬂat package; 32 leads; body 7

× 7 × 1.4 mm

SOT358-1

PCD5002A датащи(PDF) 3 Page - NXP Semiconductors

PCD5002A датащи(HTML) 3 Page - NXP Semiconductors

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48

датащи скачать

ссылки URL