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JITTER CHARACTERISTICS IN INPUT CLOCK MODE

S0246-01

CDCE421

PhaseNoise

Analyzer

150 W

150 W

150 W

50 W

XIN1

XIN2

0.1 F

m

100pF

CDCE421

SCAS842 – APRIL 2007

The jitter characterization test is performed using an LVCMOS input signal driving a CDCE421 device packaged

in the QFN-24 package.

Figure 7. Jitter Test Configuration for an LVTTL Input Driving the CDCE421

Table 4. Measured Output Jitter

LVPECL (Typical Measured Output

LVDS (Typical Measured Output

Jitter), ps

Jitter), ps

Output

Input

JRMS (12

Dj (Deter-

JRMS (12

Dj (Deter-

Pre-

Tj (Total

Tj (Total

Frequency

Frequency

VCO

Divider

kHz to 20

ministic

kHz to 20

ministic

scaler

Jitter)

Jitter)

(MHz)

(MHz)

MHz)

Jitter)

MHz)

Jitter)

100

33.3333

1

5

4

0.507

35.33

11.54

0.552

41.86

21.4

106.25

35.4167

2

5

4

0.53

30.39

11

0.564

35.38

16.01

125

31.25

1

4

4

0.529

47.47

25.2

0.561

74.14

53.51

156.25

31.25

1

3

4

0.472

31.54

9.12

0.482

42.31

23.33

212.5

35.4167

2

5

2

0.512

33.96

13.78

0.523

58.45

37.84

250

31.25

1

4

2

0.42

36.98

18.52

0.525

87.5

67.35

312.5

31.25

1

3

2

0.378

29.82

11

0.45

66.44

47.49

370

30.8333

1

5

1

0.369

29.6

12.05

0.439

69.77

51.2

400

33.3333

1

5

1

0.377

28.1

11.48

0.501

69.75

51.87

708

35.4

2

3

1

0.438

31.65

14.84

1000

31.25

1

2

1

0.456

40.34

19.66

15

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