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CDCE421 датащи(PDF) 13 Page - Texas Instruments |
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CDCE421 датащи(HTML) 13 Page - Texas Instruments |
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13 / 30 page ![]() www.ti.com OUTPUTS (LVPECL OR LVDS) ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS CDCE421 SCAS842 – APRIL 2007 The CDCE421 device has two sets of output drivers, LVPECL and LVDS, where the outputs are wire-ORed together. Only one output can be selected at a time; the other goes to the high-impedance state (Hi-Z). If the device is configured for an LVPECL, the output buffers go to Hi-Z and the termination resistors determine the state of the output (LVPECLP = LVPECLN = Hi-Z) in the device disable mode (CE = L). If the device is configured in LVDS mode, the outputs go to Hi-Z if the device is disabled (CE = L). over operating free-air temperature range (unless otherwise noted) (1) VALUE UNIT VCC Supply voltage(2) –0.5 to 4.6 V VI Voltage range for all other input pins(2) –0.5 to VCC + 0.5 V IO Output current for LVPECL –50 mA Electrostatic discharge (HBM) 2 kV TA Characterized free-air temperature range (no airflow) –40 to 85 °C TJ Maximum junction temperature 125 °C Tstg Storage temperature range –65 to 150 °C (1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under recommended operating conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. (2) All voltage values are with respect to network ground terminal. over operating free-air temperature range (unless otherwise noted) MIN TYP MAX UNIT VCC Supply voltage 3 3.3 3.6 V TA Ambient temperature (no airflow, no heat sink) –40 85 °C recommended operating conditions for CDCE421 device PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VCC Supply voltage 3 3.3 3.6 V IVCC(LVDS) Total current LVDS mode, 3.3 V, 366 MHz 73 93 mA IVCC(LVPECL) Total current consumption LVPECL mode, 3.3 V, 366 MHz 91 110 mA LVDS OUTPUT MODE (see Figure 10) fCLK Output frequency 10.9 400 MHz |VOD| LDVS differential output voltage RL = 100 Ω 240 400 454 mV ∆V OD LVDS VOD magnitude change 50 mV VOS Offset voltage –40 °C to 85°C 0.84 1.1 1.39 V ∆V OS VOS magnitude change 25 mV tr Output rise time 20% to 80% of VOUTpp 170 ps tf Output fall time 80% to 20% of VOUTpp 170 ps Short Vout+ to ground –20 mA IOS Short Vout– to ground 20 mA Duty cycle of the output waveform 46% 50% 53% 13 Submit Documentation Feedback |
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