P83C524 datasheet(32/76 Pages) PHILIPS

32 / 76 page

1997 Dec 15

Philips Semiconductors

Product speciﬁcation

8-bit microcontrollers

P83C524; P80C528; P83C528

13 BIT-LEVEL I2C INTERFACE

This bit-level serial I/O interface supports the I2C-bus (see

Fig.18). P1.6/SCL and P1.7/SDA are the serial I/O pins.

These two pins meet the I2C specification concerning the

input levels and output drive capability. Consequently,

these pins have an open drain output configuration. All

four modes of the I2C-bus are supported:

• master transmitter

• master receiver

• slave transmitter

• slave receiver.

The advantages of the bit-level I2C hardware compared

with a full software I2C implementation are:

• the hardware can generate the SCL pulse

• testing a single bit (RBF respectively, WBF) is sufficient

as a check for error free transmission.

The bit-level I2C hardware operates on serial bit level and

performs the following functions:

• filtering the incoming serial data and clock signals

• recognizing the START condition

• generating a serial interrupt request SI after reception of

a START condition and the first falling edge of the serial

clock

• recognizing the STOP condition

• recognizing a serial clock pulse on the SCL line

• latching a serial bit on the SDA line (SDI)

• stretching the SCL LOW period of the serial clock to

suspend the transfer of the next serial data bit

• setting Read Bit Finished (RBF) when the SCL clock

pulse has finished and Write Bit Finished (WBF) if there

is no arbitration loss detected (i.e. SDA = 0 while

SDO = 1)

• setting a serial clock LOW-to-HIGH detected (CLH) flag

• setting a Bus Busy (BB) flag on a START condition and

clearing this flag on a STOP condition

• releasing the SCL line and clearing the CLH, RBF and

WBF flags to resume transfer of the next serial data bit

• generating an automatic clock if the single bit data

The following functions must be done in software:

• handling the I2C START interrupts

• converting serial to parallel data when receiving

• converting parallel to serial data when transmitting

• comparing the received slave address with its own

• interpreting the acknowledge information

• guarding the I2C status if RBF or WBF = 0.

additionally, if acting as master:

• generating START and STOP conditions

• handling bus arbitration

• generating serial clock pulses if S1BIT is not used.

Three SFRs control the bit-level I2C interface: S1INT,

S1BIT and S1SCS.

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