AD9949

Rev. B | Page 18 of 36

PRECISION TIMING HIGH SPEED TIMING GENERATION

The AD9949 generates flexible high speed timing signals using

the Precision Timing core. This core is the foundation for gener-

ating the timing used for both the CCD and the AFE: the reset

gate (RG), horizontal drivers (H1 to H4), and the SHP/SHD

sample clocks. A unique architecture makes it routine for the

system designer to optimize image quality by providing precise

control over the horizontal CCD readout and the AFE corre-

lated double sampling.

TIMING RESOLUTION

The Precision Timing core uses a 1× master clock input (CLI) as

a reference. This clock should be the same as the CCD pixel

clock frequency. Figure 16 illustrates how the internal timing

core divides the master clock period into 48 steps or edge

positions. Therefore, the edge resolution of the Precision Timing

refer to the Applications Information section.

HIGH SPEED CLOCK PROGRAMMABILITY

Figure 17 shows how the high speed clocks, RG, H1 to H4,

SHP, and SHD, are generated. The RG pulse has programma-

ble rising and falling edges and may be inverted using the

polarity control. The horizontal clocks H1 and H3 have

programmable rising and falling edges and polarity control.

The H2 and H4 clocks are always inverses of H1 and H3, re-

spectively. Table 16 summarizes the high speed timing registers

and their parameters.

Each edge location setting is 6 bits wide, but only 48 valid edge

locations are available. Therefore, the register values are

mapped into four quadrants, with each quadrant containing

12 edge locations. Table 17 shows the correct register values for

the corresponding edge locations.

NOTES

1. PIXEL CLOCK PERIOD IS DIVIDED INTO 48 POSITIONS, PROVIDING FINE EDGE RESOLUTION FOR HIGH SPEED CLOCKS.

2. THERE IS A FIXED DELAY FROM THE CLI INPUT TO THE INTERNAL PIXEL PERIOD POSITIONS (

P[0]

P[48] = P[0]

P[12]

P[24]

P[36]

1 PIXEL

PERIOD

...

...

CLI

POSITION

Figure 16. High Speed Clock Resolution from CLI Master Clock Input

H1/H3

H2/H4

CCD SIGNAL

RG

12

3

4

56

PROGRAMMABLE CLOCK POSITIONS:

1. RG RISING EDGE.

2. RG FALLING EDGE.

3. SHP SAMPLE LOCATION.

4. SHD SAMPLE LOCATION.

5. H1/H3 RISING EDGE POSITION6. H1/H3 FALLING EDGE POSITION (H2/H4 ARE INVERSE OF H1/H3).

Figure 17. High Speed Clock Programmable Locations