AD9949

Rev. B | Page 12 of 36

SERIAL INTERFACE TIMING

The AD9949’s internal registers are accessed through a 3-wire

serial interface. Each register consists of an 8-bit address and a

24-bit data-word. Both the 8-bit address and 24-bit data-word

are written starting with the LSB. To write to each register, a

32-bit operation is required, as shown in Figure 14. Although

many registers are less than 24 bits wide, all 24 bits must be

written for each register. If the register is only 16 bits wide, then

the upper eight bits may be filled with zeros during the serial

write operation. If fewer than 24 bits are written, the register

will not be updated with new data.

Figure 15 shows a more efficient way to write to the registers by

using the AD9949’s address auto-increment capability. Using

this method, the lowest desired address is written first, followed

by multiple 24-bit data-words. Each new 24-bit data-word is

written automatically to the next highest register address. By

eliminating the need to write each 8-bit address, faster register

loading is achieved. Address auto-increment may be used start-

ing with any register location and may be used to write to as few

as two registers or as many as the entire register space.

SDATA

A0

A1

A2

A4

A5

A6

A7

D0

D1

D2

D3

D21

D22

D23

SCK

SL

A3

NOTES

1. INDIVIDUAL SDATA BITS ARE LATCHED ON SCK RISING EDGES.

2. ALL 32 BITS MUST BE WRITTEN: 8 BITS FOR ADDRESS AND 24 BITS FOR DATA.

3. IF THE REGISTER LENGTH IS <24 BITS, THEN DON’T CARE BITS MUST BE USED TO COMPLETE THE 24-BIT DATA LENGTH.

4. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.

5. VD/HD UPDATE POSITION MAY BE DELAYED TO ANY HD FALLING EDGE IN THE FIELD USING THE UPDATE REGISTER.

VD

SL UPDATED

VD/HD UPDATED

HD

...

...

...

...

...

8-BIT ADDRESS

24-BIT DATA

1

32

2

3

4

5

6

7

8

9

10

11

12

30

31

Figure 14. Serial Write Operation

SDATA

A0

A1

A2

A4

A5

A6

A7

D0

D1

D22

D23

SCK

SL

A3

NOTES

1. MULTIPLE SEQUENTIAL REGISTERS MAY BE LOADED CONTINUOUSLY.

2. THE FIRST (LOWEST ADDRESS) REGISTER ADDRESS IS WRITTEN, FOLLOWED BY MULTIPLE 24-BIT DATA-WORDS.

3. THE ADDRESS WILL AUTOMATICALLY INCREMENT WITH EACH 24-BIT DATA-WORD (ALL 24 BITS MUST BE WRITTEN).

4. SL IS HELD LOW UNTIL THE LAST DESIRED REGISTER HAS BEEN LOADED.

5. NEW DATA IS UPDATED AT EITHER THE SL RISING EDGE OR AT THE HD FALLING EDGE AFTER THE NEXT VD FALLING EDGE.

D0

D1

D22

D23

D0

...

...

...

DATA FOR STARTING

REGISTER ADDRESS

DATA FOR NEXT

REGISTER ADDRESS

D2

D1

...

...

...

...

...

...

1

32

23

45

6

7

89

10

31

34

33

56

55

58

57

59

Figure 15. Continuous Serial Write Operation