AM41PDS3228DB10IS datasheet(4/59 Pages) AMD

4 / 59 page

May 13, 2002

Am41PDS3228D

P R E L IMINARY

TABLE OF CONTENTS

Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 5

MCP Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . 5

Flash Memory Block Diagram. . . . . . . . . . . . . . . . 6

Connection Diagram . . . . . . . . . . . . . . . . . . . . . . . . 7

Special Package Handling Instructions .................................... 7

Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 9

MCP Device Bus Operations. . . . . . . . . . . . . . . . 10

Table 1. Device Bus Operations—SRAM Word Mode, CIOs = V

CC 10

Table 2. Device Bus Operations—SRAM Byte Mode, CIOs = V

Flash Device Bus Operations . . . . . . . . . . . . . . . 12

Requirements for Reading Array Data ................................... 12

Read Mode ............................................................................. 12

Random Read (Non-Page Mode Read) .............................. 12

Page Mode Read .................................................................... 12

Table 3. Page Word Mode ..............................................................12

Writing Commands/Command Sequences ............................ 12

Accelerated Program Operation .......................................... 12

Autoselect Functions ........................................................... 13

Simultaneous Read/Write Operations with Zero Latency ....... 13

Standby Mode ........................................................................ 13

Automatic Sleep Mode ........................................................... 13

RESET#: Hardware Reset Pin ............................................... 13

Output Disable Mode .............................................................. 14

Table 4. Am29PDS322DT Top Boot Sector Addresses ..................14

Table 5. Am29PDS322DT Top Boot SecSi Sector Address ...........15

Table 6. Am29PDS322DB Bottom Boot Sector Addresses ............15

Am29PDS322DB Bottom Boot SecSi Sector Address.................... 17

Autoselect Mode ..................................................................... 17

Sector/Sector Block Protection and Unprotection .................. 17

Table 8. Top Boot Sector/Sector Block Addresses for Protection/Un-

protection ........................................................................................17

Table 9. Bottom Boot Sector/Sector Block Addresses for Protec-

tion/Unprotection .............................................................................18

Write Protect (WP#) ................................................................ 18

Temporary Sector/Sector Block Unprotect ............................. 18

Figure 1. Temporary Sector Unprotect Operation........................... 19

Figure 2. In-System Sector/Sector Block Protect and Unprotect Algo-

rithms .............................................................................................. 20

SecSi (Secured Silicon) Sector Flash Memory Region .......... 21

Factory Locked: SecSi Sector Programmed and Protected

at the Factory ...................................................................... 21

Hardware Data Protection ...................................................... 21

Low V

CC Write Inhibit ........................................................... 21

Write Pulse “Glitch” Protection ............................................ 22

Logical Inhibit ...................................................................... 22

Power-Up Write Inhibit ......................................................... 22

Flash Command Definitions . . . . . . . . . . . . . . . . 22

Reading Array Data ................................................................ 22

Reset Command ..................................................................... 22

Autoselect Command Sequence ............................................ 22

Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 23

Word Program Command Sequence ..................................... 23

Unlock Bypass Command Sequence .................................. 23

Figure 3. Unlock Bypass Algorithm ................................................. 24

Figure 4. Program Operation .......................................................... 24

Chip Erase Command Sequence ........................................... 24

Sector Erase Command Sequence ........................................ 25

Erase Suspend/Erase Resume Commands ........................... 25

Figure 5. Erase Operation.............................................................. 26

Table 10. Am29PDS322D Command Definitions ........................... 27

Flash Write Operation Status . . . . . . . . . . . . . . . 28

DQ7: Data# Polling ................................................................. 28

Figure 6. Data# Polling Algorithm .................................................. 28

RY/BY#: Ready/Busy# ............................................................ 29

DQ6: Toggle Bit I .................................................................... 29

Figure 7. Toggle Bit Algorithm........................................................ 29

DQ2: Toggle Bit II ................................................................... 30

Reading Toggle Bits DQ6/DQ2 ............................................... 30

DQ5: Exceeded Timing Limits ................................................ 30

DQ3: Sector Erase Timer ....................................................... 30

Table 11. Write Operation Status ................................................... 31

Absolute Maximum Ratings . . . . . . . . . . . . . . . . 32

Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 32

Industrial (I) Devices ............................................................ 32

CCf/VCCs Supply Voltage ................................................... 32

Flash DC Characteristics . . . . . . . . . . . . . . . . . . 33

CMOS Compatible .................................................................. 33

SRAM DC and Operating Characteristics . . . . . 34

Figure 10. I

CC1 Current vs. Time (Showing Active and Automatic

Sleep Currents) .............................................................................. 35

Figure 11. Typical ICC1 vs. Frequency ............................................ 35

Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . 36

Figure 12. Test Setup.................................................................... 36

Table 12. Test Specifications ......................................................... 36

Key To Switching Waveforms . . . . . . . . . . . . . . . 36

Figure 13. Input Waveforms and Measurement Levels ................. 36

AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 37

SRAM CE#s Timing ................................................................ 37

Figure 14. Timing Diagram for Alternating

Between SRAM to Flash ................................................................ 37

Figure 15. Conventional Read Operation Timings ......................... 38

Figure 16. Page Mode Read Timings ............................................ 39

Hardware Reset (RESET#) .................................................... 40

Figure 17. Reset Timings ............................................................... 40

Flash Erase and Program Operations .................................... 41

Figure 18. Program Operation Timings.......................................... 42

Figure 19. Accelerated Program Timing Diagram.......................... 42

Figure 20. Chip/Sector Erase Operation Timings .......................... 43

Figure 21. Back-to-back Read/Write Cycle Timings ...................... 44

Figure 22. Data# Polling Timings (During Embedded Algorithms). 44

Figure 23. Toggle Bit Timings (During Embedded Algorithms)...... 45

Figure 24. DQ2 vs. DQ6................................................................. 45

Temporary Sector/Sector Block Unprotect ............................. 46

Figure 25. Temporary Sector/Sector Block Unprotect

Timing Diagram.............................................................................. 46

Figure 26. Sector/Sector Block Protect and Unprotect

Timing Diagram.............................................................................. 47

Alternate CE#f Controlled Erase and Program Operations .... 48

Figure 27. Flash Alternate CE#f Controlled Write (Erase/Program) Op-

eration Timings............................................................................... 49

SRAM AC Characteristics . . . . . . . . . . . . . . . . . . 50

Read Cycle ............................................................................. 50

Figure 28. SRAM Read Cycle—Address Controlled...................... 50

Figure 29. SRAM Read Cycle ........................................................ 51

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