AM29DL400B datasheet(18/47 Pages) AMD

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Am29DL400B

3. Note: See Table 5 for program command sequence.

Figure 3. Program Operation

Chip Erase Command Sequence

Chip erase is a six bus cycle operation. The chip

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock write cycles are then followed by

the chip erase command, which in turn invokes the

Embedded Erase algorithm. The device does not re-

quire the system to preprogram prior to erase. The

Embedded Erase algorithm automatically prepro-

grams and verifies the entire memory for an all zero

data pattern prior to electrical erase. The system is

not required to provide any controls or timings dur-

ing these operations. Table 5 shows the address and

data requirements for the chip erase command

sequence.

When the Embedded Erase algorithm is complete,

that bank returns to reading array data and ad-

dresses are no longer latched. The system can

determine the status of the erase operation by using

DQ7, DQ6, DQ2, or RY/BY#. Refer to the Write Oper-

ation Status section for information on these status

bits.

Any commands written during the chip erase opera-

tion are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the chip erase command sequence

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

Figure 4 illustrates the algorithm for the erase opera-

tion. Refer to the Erase and Program Operations

tables in the AC Characteristics section for parame-

ters, and Figure 18 section for timing diagrams.

Sector Erase Command Sequence

Sector erase is a six bus cycle operation. The sector

erase command sequence is initiated by writing two

unlock cycles, followed by a set-up command. Two

additional unlock cycles are written, and are then fol-

lowed by the address of the sector to be erased, and

the sector erase command. Table 5 shows the ad-

dress and data requirements for the sector erase

command sequence.

The device does not require the system to prepro-

gram prior to erase. The Embedded Erase algorithm

automatically programs and verifies the entire mem-

ory for an all zero data pattern prior to electrical

erase. The system is not required to provide any

controls or timings during these operations.

After the command sequence is written, a sector

erase time-out of 50 µs occurs. During the time-out

period, additional sector addresses and sector erase

commands may be written. Loading the sector erase

buffer may be done in any sequence, and the num-

ber of sectors may be from one sector to all sectors.

The time between these additional cycles must be

less than 50 µs, otherwise the last address and com-

mand may not be accepted, and erasure may begin.

It is recommended that processor interrupts be dis-

abled during this time to ensure all commands are

accepted. The interrupts can be re-enabled after the

last Sector Erase command is written. Any com-

mand other than Sector Erase or Erase Suspend

during the time-out period resets that bank to

reading array data. The system must rewrite the

command sequence and any additional addresses

and commands.

The system can monitor DQ3 (in the erasing bank)

to determine if the sector erase timer has timed out

(See the section on DQ3: Sector Erase Timer.). The

time-out begins from the rising edge of the final

WE# pulse in the command sequence.

When the Embedded Erase algorithm is complete,

the bank returns to reading array data and ad-

dresses are no longer latched. Note that while the

Embedded Erase operation is in progress, the system

can read data from the non-erasing bank. The sys-

tem can determine the status of the erase operation

by reading DQ7, DQ6, DQ2, or RY/BY# in the erasing

bank. Refer to the Write Operation Status section for

information on these status bits.

Once the sector erase operation has begun, only the

Erase Suspend command is valid. All other com-

mands are ignored. However, note that a hardware

reset immediately terminates the erase operation. If

that occurs, the sector erase command sequence

should be reinitiated once that bank has returned to

reading array data, to ensure data integrity.

START

Write Program

Command Sequence

Data Poll

from System

Verify Data?

Yes

Last Address?

Yes

Programming

Completed

Increment Address

Embedded

Program

algorithm

in progress

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