Data Sheet

ADL7078

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 6 of 19

Figure 2. Pin Configuration

Table 8. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

RBIAS

Bias Setting Resistor. Connect a resistor between RBIAS and VDD to set the IDQ. See Figure 3 for the interface schematic.

2, 6 to 14, 18 to 23

NIC

Not Internally Connected. This pin is not connected internally. For normal operation, connect the NIC pins to a ground plane that has

low electrical and thermal impedance.

3, 5, 15, 17

GND

Ground. Connect the GND pins to a ground plane that has low electrical and thermal impedance. See Figure 4 for the interface

schematic.

4

RFIN

RF Input. The RFIN pin has a DC path to ground followed by an AC-coupling capacitor in the RF signal path and matched to 50 Ω. If

the DC bias level of the input signal is not equal to 0 V, externally AC-couple the RFIN pin. See Figure 5 for the interface schematic.

16

RFOUT

RF Output. The RFOUT pin has a resistive path to ground and an AC-coupling capacitor in the RF signal path and matched to 50

Ω. If the DC bias level of the next stage is not equal to 0 V, externally AC-couple the RFOUT pin. See Figure 5 for the interface

schematic.

24

VDD

Drain Bias. Connect the VDD pin to the supply voltage. See Figure 6 for the interface schematic.

EXPOSED

PADDLE

Exposed Ground Paddle. Connect the exposed paddle to a ground plane that has low electrical and thermal impedance.

INTERFACE SCHEMATICS

Figure 3. RBIAS Interface Schematic

Figure 4. GND Interface Schematic

Figure 5. RFIN/RFOUT Interface Schematic

Figure 6. VDD Interface Schematic