TMS320F datasheet(28/389 Pages) TI

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Memory

2-5

Architectural Overview

2.3

Memory

The ’C24x contains the following types of on-chip memory:

- Dual-access RAM (DARAM)

- Flash EEPROM or ROM (masked)

The ’C24x memory is organized into four individually-selectable spaces:

- Program (64K words)

- Local data (64K words)

- Global data (32K words)

- Input/Output (64K words)

These spaces form an address range of 224K words.

2.3.1

On-Chip Dual-Access RAM (DARAM)

The ’C24x has 544 words of on-chip DARAM, which can be accessed twice

per machine cycle. This memory is primarily intended to hold data, but when

needed, can also be used to hold programs. The memory can be configured

in one of two ways, depending on the state of the CNF bit in status register ST1.

- When CNF = 0, all 544 words are configured as data memory.

- When CNF = 1, 288 words are configured as data memory and 256 words

are configured as program memory.

Because DARAM can be accessed twice per cycle, it improves the speed of

the CPU. The CPU operates within a 4-cycle pipeline. In this pipeline, the CPU

reads data on the third cycle and writes data on the fourth cycle. However,

DARAM allows the CPU to write and read in one cycle; the CPU writes to

DARAM on the master phase of the cycle and reads from DARAM on the slave

phase. For example, suppose two instructions, A and B, store the accumulator

value to DARAM and load the accumulator with a new value from DARAM.

Instruction A stores the accumulator value during the master phase of the CPU

cycle, and instruction B loads the new value in the accumulator during the

slave phase. Because part of the dual-access operation is a write, it only

applies to RAM.

TMS320F датащи(PDF) 28 Page - Texas Instruments