TMS320F datasheet(63/389 Pages) TI

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External Memory Interface Operation

4-19

Central Processing Unit

The R/W signal goes high at least one-half cycle of CLKOUT before any read

cycle; for contiguous read cycles, STRB stays low. At the end of a read cycle

or sequence of reads, STRB and RD go high on the falling edge of CLKOUT.

Write cycles always have at least one inactive (pad) cycle of CLKOUT before

and after the actual write operation, including contiguous writes. This allows

a smooth transition between the write and any adjacent bus operations or oth-

er writes. For this pad cycle, STRB and WE are always high. The R/W signal

always changes state on the rising edge of CLKOUT during the pad cycle be-

fore and after a write or series of writes. This prevents bus contention during

a transition between read and write operations. Note that for a series of writes,

R/W stays low.

Timing of valid addresses for writes differs, depending on what activities occur

before and after the write. Between writes, and for the first and last write in a

series, ADDRESS becomes valid on the rising edge of CLKOUT. If a read im-

mediately follows a write or series of writes, ADDRESS becomes valid for that

read cycle one half-cycle of CLKOUT early — that is, on the rising edge, rather

than on the falling edge, of CLKOUT. This is an exception to the usual read

cycle address timing.

For the actual write operation, STRB and WE both go low on the falling edge

of CLKOUT and stay low until the next falling edge of CLKOUT (for 0-wait-state

write cycles). For 1-wait-state (multicycle) writes, STRB and WE remain low

but go high again on the falling edge of CLKOUT at the beginning of the pad

cycle.

Write data is driven approximately at the falling edge of STRB and WE

and is held for approximately one half-cycle of CLKOUT after STRB and WE

go high (refer to the TMS320C24x data sheet for actual timing specifications).

Transitions on the external parallel interface control outputs (CLKOUT, STRB,

WE, and RD) are all initiated by the same internal clocks. Since these signals

also use the same output buffer circuitry, they all switch within close tolerances

of each other, as specified in the TMS320C24x data sheet.

Transitions on the address bus and other related outputs (IS, PS, DS, R/W, and

BR) are initiated by the same internal signals that cause transitions on the con-

trol outputs; however, the internal device logic that generates these outputs is

different from the circuitry used for the control outputs. Therefore, transitions

on the address bus and related outputs typically occur later than control-line

transitions.

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