SC1933C datasheet(15/28 Pages) POWERINT

15 / 28 page

Rev. C 11/18

SC1933C/SC1936C

www.power.com

Layout Example

Figure 14. PCB Layout.

Recommendations for EMI Reduction

1. Appropriate component placement and small loop areas of the

primary and secondary power circuits help minimize radiated and

conducted EMI. Care should be taken to achieve a compact loop

area.

2. A small capacitor in parallel to the clamp diode on the primary-

side can help reduce radiated EMI.

3. A resistor in series with the bias winding helps reduce radiated

EMI.

4. Common mode chokes are typically required at the input of the

power supply to sufficiently attenuate common mode noise.

However the same performance can be achieved by using shield

windings on the transformer. Shield windings can also be used in

conjunction with common mode filter inductors at input to

improve conducted and radiated EMI margins.

5. Adjusting SR FET RC snubber component values can help reduce

high frequency radiated and conducted EMI.

6. A pi-filter comprising differential inductors and capacitors can be

used in the input rectifier circuit to reduce low frequency

differential EMI.

7. A 1 mF ceramic capacitor connected at the output of the power

supply helps to reduce radiated EMI.

Recommendations for Transformer Design

Transformer design must ensure that the power supply delivers the

rated power at the lowest input voltage. The lowest voltage on the

rectified DC bus depends on the capacitance of the filter capacitor

used. At least 2 mF/W is recommended to always keep the DC bus

voltage above 70 V, though 3 mF/W provides sufficient margin. The

ripple on the DC bus should be measured to confirm the design

calculations for transformer primary-winding inductance selection.

PI-8868-102618

Keep Feedback pin

decoupling capacitor

close to the IC

Keep IS-GND pin

sense resistor close

to output capacitor

and output connector.

Keep IS-GND pin

decoupling capacitor

close to the IC

Keep output SR FET

and output filter

capacitor loop short

Place forward and

feedback sense resistors

near the IC

Maximize Drain area of SR FET

for good heat sinking

6.5 mm spark gap

Maximize source area for good heat sinking

Y capacitor connection to the plus bulk rail

on the primary-side for surge protection

Keep Drain and clamp loop short; keep drain

components away from BPP and V pin circuitry

Keep BPP and BPS Capacitors near the IC

PCB – Bottom Side

Place VOLTAGE pin sense resistor

close to the IC

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