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поискавой системы для электроныых деталей |
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поискавой системы для электроныых деталей |
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TPS274C65AS датащи(PDF) 13 Page - Texas Instruments |
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TPS274C65AS датащи(HTML) 13 Page - Texas Instruments |
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13 / 87 page  7.6 Switching Characteristics VS = 6 V to 36 V, TJ = –40°C to +125°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT tDR CH1 and CH2 Turnon delay time VS = 24 V, RL = 48 Ω 50% of EN to 10% of VOUT 5 18 25 µs tDF CH1 and CH2 Turnoff delay time VS = 24 V, RL = 48 Ω 50% of EN to 90% of VOUT 16 24 33 µs SR2R VOUTx rising slew rate VS = 24 V, 25% to 75% of VOUT, RL = 48 Ω, 1 1.6 2.2 V/µs SR2F VOUTx falling slew rate VS = 24 V, 75% to 25% of VOUT, RL = 48 Ω, 1 1.4 1.8 V/µs fmax Maximum PWM frequency 1 kHz tON CHx Turnon time VS = 24 V, RL = 48 Ω 50% of EN to 90% of VOUT 33 42 µs tOFF CHx Turnoff time VS = 24 V, RL = 48 Ω 50% of EN to 10% of VOUT 46 57 µs tON - tOFF CHx Turnon and off matching 1ms ON time switch enable pulse VBB = 24 V, RL = 48 Ω –41 –7 23 µs tON - tOFF CHx Turnon and off matching 100-µs OFF time switch enable pulse, VS = 24 V, RL = 48 Ω, F = fmax –41 –7 23 µs tON - tOFF CHxTurnon and off matching 100-µs ON time switch enable pulse, VS = 24 V, RL = 48 Ω, F = fmax –41 –7 23 µs ΔPWM CHx PWM accuracy - average load current 200-µs enable pulse, VS = 24 V, RL = 48 Ω F = fmax –20 20 % 7.7 SPI Timing Requirements Over operating junction temperature TJ = –40°C to 125°C and operating VVS = 2.3 to 36 V (unless otherwise noted). MIN NOM MAX UNIT tSPI SPI clock (SCLK) period CSDO = 30 pF; 100 ns thigh High time: SCLK logic high-time duration 45 ns tlow Low time: SCLK logic low-time duration 45 ns tsucs NCS setup time: Time delay between falling edge of NCS and rising edge of SCLK 45 ns tsu_SDI SDI setup time: Setup time of SDI before the falling edge of SCLK 15 ns th_SDI SDI hold time: Hold time of SDI before the falling edge of SCLK 30 ns td_SDO Delay time: Time delay from rising edge of SCLK to data valid at SDO 30 ns thcs Hold time: Time between the falling edge of SCLK and rising edge of NCS 45 ns tdis_cs nCS disable time, nCS high to SDO high impedance 10 ns thics SPI transfer inactive time (time between two transfers) during which NCS must remain high 500 ns www.ti.com TPS274C65 SLVSFZ2B – APRIL 2023 – REVISED OCTOBER 2023 Copyright © 2023 Texas Instruments Incorporated Submit Document Feedback 13 Product Folder Links: TPS274C65 |
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