DESCRIPTION

s 3.0ns typical propagation delay

s <500ps typical output-to-output skew

s Differential PECL inputs

s 24mA TTL outputs

s Flow-through pinouts

s Available in 8-pin SOIC package

The SY10/100ELT23 are dual differential PECL-to-TTL

translators. Because PECL (Positive ECL) levels are

used, only +5V and ground are required. The small outline

8-lead SOIC package and the low skew dual gate design

of the ELT23 makes it ideal for applications which require

the translation of a clock and a data signal.

The ELT23 is available in both ECL standards: the

10ELT is compatible with positive ECL 10H logic levels,

while the 100ELT is compatible with positive ECL 100K

logic levels.

FEATURES

DUAL DIFFERENTIAL

PECL-to-TTL

TRANSLATOR

PIN NAMES

PIN CONFIGURATION/BLOCK DIAGRAM

Pin

Function

TTL Outputs

Differential PECL Inputs

+5.0V Supply

GND

Ground

SOIC

TOP VIEW

Precision Edge™

SY10ELT23

SY100ELT23

FINAL

1

2

3

4

5

6

7

8

GND

PECL

TTL

1

Rev.: I

Amendment: 0

Issue Date:

February 2003

Precision Edge is a trademark of Micrel, Inc.

Precision Edge™