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3946 датащи(PDF) 7 Page - Allegro MicroSystems |
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3946 датащи(HTML) 7 Page - Allegro MicroSystems |
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7 / 13 page ![]() 7 Worcester, Massachusetts 01615-0036 (508) 853-5000 115 Northeast Cutoff, Box 15036 www.allegromicro.com 3946 Half-Bridge Power MOSFET Controller Application Information Bootstrap Capacitor Selection . C BOOT must be cor- rectly selected to ensure proper operation of the device. If too large, time is wasted charging the capacitor, with the result being a limit on the maximum duty cycle and PWM frequency. If the capacitor is too small, the voltage drop can be too large at the time the charge is transferred from the C BOOT to the MOSFET gate. To keep the voltage drop small: Q BOOT >> QGATE where a factor in the range of 10 to 20 is reasonable. Using 20 as the factor: Q BOOT = CBOOT × VBOOT = QGATE × 20 and C BOOT = QGATE × 20 / VBOOT The voltage drop on the BOOT pin, as the MOSFET is being turned on, can be approximated by: Delta_v = Q GATE / CBOOT For example, given a gate charge, Q GATE, of 160 nC, and the typical BOOT pin voltage of 12 V, the value of the Boot capacitor, C BOOT, can be determined by: C BOOT = (160 nC × 20) / 12 V ≈ 0.266 μF Therefore, a 0.22 μF ceramic (X7R) capacitor can be chosen for the Boot capacitor. In that case, the voltage drop on the BOOT pin, when the high-side MOSFET is turned on, is: Delta_v = 160 nC / 0.22 μF = 0.73 V Bootstrap Charging. It is good practice to ensure that the high-side bootstrap capacitor is completely charged before a high-side PWM cycle is requested. The time required to charge the capacitor can be approxi- mated by: t CHARGE = CBOOT (Delta_v / 100 mA) At power-up and when the drivers have been disabled for a long time, the bootstrap capacitor can be completely discharged. In this case, Delta_v can be considered to be the full high-side drive voltage, 12 V. Otherwise, Delta_v is the amount of voltage dropped during the charge transfer, which should be 400 mV or less. The capacitor is charged whenever the S pin is pulled low, via a GL PWM cycle, and current flows from VREG through the internal bootstrap diode circuit to C BOOT. Power Dissipation. For high ambient temperature applications, there may be little margin for on-chip power consumption. Careful attention should be paid to ensure that the operating conditions allow the A3946 to remain in a safe range of junction temperature. The power consumed by the A3946 can be estimated as: P_total = Pd_bias + Pd_cpump + Pd_switching_loss where: Pd_bias = V BB × IVBB , typically 3 mA, and Pd_cpump = (2V BB – VREG) IAVE, for VBB < 15 V, or Pd_cpump = (V BB – VREG) IAVE, for VBB > 15 V, in either case, where I AVE = QGATE × 2 × fPWM and Pd_switching_loss = Q GATE × VREG × 2 × fPWM Ratio, where Ratio = 10 Ω / (R GATE + 10 Ω). |
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