1

SY10E212

SY100E212

Micrel, Inc.

M9999-032206

hbwhelp@micrel.com or (408) 955-1690

DESCRIPTION

FEATURES

s Scannable version E112 driver

s 1025ps max. CLK to Output

s Dual differential outputs

s Master Reset

s Internal 75K

s Fully compatible with industry standard 10KH,

100K ECL levels

s Fully compatible with Motorola MC10E/100E212

s Available in 28-pin PLCC package

The SY10/100E212 are scannable registered ECL

drivers typically used as fan-out memory address drivers

for ECL cache driving. In a VLSI array-based CPU design,

use of the E212 allows the user to conserve array output

cell functionality and also output pins.

The input shift register is designed with control logic

which greatly facilitates its use in boundary scan

applications.

3-BIT SCANNABLE

REGISTER

SY10E212

SY100E212

BLOCK DIAGRAM

D

Q

D

Q

D

Q

S-OUT

S-IN

LOAD

SHIFT

CLK

MR

Pin

Function

Data Inputs

S-IN

Scan Input

LOAD

LOAD/HOLD Control

SHIFT

Scan Control

CLK

Clock

MR

Master Reset

S-OUT

Scan Output

Q[0:2]a, Q[0:2]b

True Outputs

Q[0:2]a, Q[0:2]b

Inverting Outputs

PIN NAMES

Rev.: F

Amendment: /0

Issue Date:

March 2006