UJA1069 datasheet(6/64 Pages) PHILIPS

6 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

6 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

5.2 Pin description

Table 2.

Pin description

Symbol

Description

HTSSOP32 HTSSOP24

n.c.

not connected

n.c.

not connected

TXDL

LIN transmit data input (LOW for dominant, HIGH for

recessive)

voltage regulator output for the microcontroller (3 V, 3.3 V

or 5 V depending on the SBC version)

RXDL

LIN receive data output (LOW when dominant, HIGH

when recessive)

RSTN

reset output to microcontroller (active LOW; will detect

clamping situations)

INTN

interrupt output to microcontroller (active LOW;

open-drain, wire-AND this pin to other ECU interrupt

outputs)

enable output (active HIGH; push-pull, LOW with every

reset / watchdog overﬂow)

SDI

SPI data input

SDO

SPI data output (ﬂoating when pin SCS is HIGH)

SCK

SPI clock input

SCS

SPI chip select input (active LOW)

n.c.

not connected

n.c.

not connected

n.c.

not connected

TEST

test pin (should be connected to ground in application)

INH/LIMP

inhibit / limp home output (BAT14 related, push-pull,

default ﬂoating)

WAKE

local wake-up input (BAT42 related, continuous or cyclic

sampling)

n.c.

not connected

n.c.

not connected

n.c.

not connected

n.c.

not connected

GND

ground

n.c.

not connected

LIN

LIN bus line (LOW in dominant state)

RTLIN

LIN-bus termination resistor connection

BAT14

14 V battery supply input

n.c.

not connected

SYSINH

system inhibit output (BAT42 related; e.g. for controlling

external DC-to-DC converter)

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