UJA1069 datasheet(54/64 Pages) PHILIPS

54 / 64 page

UJA1069_2

Preliminary data sheet

Rev. 02 — 5 March 2007

54 of 64

NXP Semiconductors

UJA1069

LIN fail-safe system basis chip

10. Dynamic characteristics

Table 26.

Dynamic characteristics

Tvj = −40 °C to +150 °C; VBAT42 =5.5 V to52V; VBAT14 =5.5 V to27V; VBAT42 ≥ VBAT14 − 1 V; unless otherwise speciﬁed. All

voltages are deﬁned with respect to ground. Positive currents ﬂow into the IC.[1]

Symbol

Parameter

Conditions

Min

Typ

Max

Unit

Serial peripheral interface timing; pins SCS, SCK, SDI and SDO (see Figure 24)[2]

Tcyc

clock cycle time

960

tlead

enable lead time

clock is low when SPI select

falls

240

tlag

enable lag time

clock is low when SPI select

rises

240

tSCKH

clock HIGH time

480

tSCKL

clock LOW time

480

tsu

input data setup time

input data hold time

400

tDOV

output data valid time

pin SDO; CL = 10 pF

400

tSSH

SPI select HIGH time

480

LIN transceiver; pins LIN, TXDL and RXDL[3]

δ1

duty cycle 1

Vth(reces)(max) = 0.744 × VBAT42;

Vth(dom)(max) = 0.581 × VBAT42;

LSC = 0; tbit =50 µs;

VBAT42 = 7 V to 18 V

[4] 0.396

δ2

duty cycle 2

Vth(reces)(min) = 0.422 × VBAT42;

Vth(dom)(min) = 0.284 × VBAT42;

LSC = 0; tbit =50 µs;

VBAT42 = 7.6 V to 18 V

[5] -

0.581

δ3

duty cycle 3

Vth(reces)(max) = 0.778 × VBAT42;

Vth(dom)(max) = 0.616 × VBAT42;

LSC = 1; tbit =96 µs;

VBAT42 = 7 V to 18 V

[4] 0.417

δ4

duty cycle 4

Vth(reces)(min) = 0.389 × VBAT42;

Vth(dom)(min) = 0.251 × VBAT42;

LSC = 1; tbit =96 µs;

VBAT42 = 7.6 V to 18 V

[5] -

0.590

tp(rx)

propagation delay of

receiver

CRXDL =20pF

µs

tp(rx)(sym)

symmetry of receiver

propagation delay

rising edge with respect to

falling edge; CRXDL =20pF

−2-

µs

tBUS(LIN)

minimum dominant time for

wake-up of the

LIN-transceiver

Off-line mode

150

µs

tLIN(dom)(det)

continuously dominant

clamped LIN-bus detection

time

Active mode; LIN = 0 V

160

tLIN(dom)(rec)

continuously dominant

clamped LIN-bus recovery

time

Active mode

0.8

2.2

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