TSS461C datasheet(6/57 Pages) ATMEL

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TSS461C

4193G–AUTO–12/04

Microprocessor

Interface

The processor controls the TSS461C by reading and writing the internal registers of the

circuit. These registers appear to the processor as regular memory locations.

Interface Modes

The TSS461C must be plugged in an Intel or Motorola environment with an 8-bit

address/data bus multiplexed.

Table 1. Access Mode Logic

In Intel environment, access operations need CS active, a read one with RD active, a

write one with WR active. If TSS461C is the single peripheral in the processor space,

CS can be wired to VCC.

In Motorola environment, the RD pin is wired to VSS and the access operations are

driven by CS (E). Contrary to Intel mode, CS (E) must never be wired to VCC even if the

TSS461C is alone.

To switch on-the-fly from one mode to the other, CS must be inactive.

Intel Mode

The Intel mode interface consists of 13 pins. 8 pins are the multiplexed address and

data bus, and the rest are the address strobe, the read and write commands, the chip

select and the interrupt request pins.

To access the memory locations in Intel mode, the processor must first assert a valid

address on the multiplexed address and data bus and drive the address strobe pin high.

When the required setup time has passed, the processor must drive the address strobe

low, and keep the address valid for the required hold time.

The processor must then either assert the data to be written on the address and data

bus, if a write is intended, or float the data bus for a read. The next step is to drive either

the write or read command pins low, according to the function required, and at the same

time drive the chip select pin high.

The TSS461C access cycle is then terminated by driving the chip select and command

pins low.

Note:

that the chip select pin may be driven high for the entire access cycle, and may also

remain high during and after the termination of the cycle.

CS (E)

WR (R/W)

Operation Mode

No operation

Write Operation in Motorola mode

Read operation in both modes

Write operation in Intel mode

No operation

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