TSS461C datasheet(27/57 Pages) ATMEL

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TSS461C

4193G–AUTO–12/04

•

The Transmission In Progress (TIP) tells the diagnostic system to enable

transmission diagnosis.

ESDC: Enable System

Diagnosis Clock

One: Enable SDC divider.

Zero: Disable SDC divider.

•

The Synchronous Diagnosis Clock (SDC) controls the cycle time of the

synchronous diagnosis.

Command Register (0x03)

•

Write only register.

•

Reserved: Bit 1, 2. These bits cannot be set by the user; a zero must always be

written to these bit.

•

If the circuit is operating at low bit rates, there might be a considerable delay

between the writing of this register and the performing of the actual command (worst

case 6 timeslots). The user must verify, by reading the Line Status Register (0x04),

that the commands have been performed.

GRES: General Reset

The Reset circuit command bit performs, if set, exactly as if the external reset pin was

asserted. This command bit has its own auto-reset circuitry.

One: Reset active

Zero: Reset inactive

SLEEP: Sleep Command

If the user sets the Sleep bit, the circuit will enter sleep mode. When the circuit

sleep mode, all non-user registers are setup to minimize power consumption and the

oscillator is stopped. To exit from this mode, the user must set either the idle or activate

commands.

One: Sleep active

Zero: Sleep inactive

7654321

GRES

SLEEP

IDLE

ACTI

REAR

MSDC

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