AT89LP216-20PI datasheet(18/90 Pages) ATMEL

18 / 90 page

3621A–MICRO–6/06

AT89LP216 [Preliminary]

12. Interrupts

The AT89LP216 provides 7 interrupt sources: two external interrupts, two timer interrupts, a

serial port interrupt, a general-purpose interrupt, and an analog comparator interrupt. These

interrupts and the system reset each have a separate program vector at the start of the program

memory space. Each interrupt source can be individually enabled or disabled by setting or clear-

ing a bit in the interrupt enable register IE. The IE register also contains a global disable bit, EA,

which disables all interrupts.

Each interrupt source (with the exception of the Analog Comparator) can be individually pro-

grammed to one of four priority levels by setting or clearing bits in the interrupt priority registers

IP and IPH. The Analog Comparator is fixed at the lowest priority level. An interrupt service rou-

tine in progress can be interrupted by a higher priority interrupt, but not by another interrupt of

the same or lower priority. The highest priority interrupt cannot be interrupted by any other inter-

rupt source. If two requests of different priority levels are pending at the end of an instruction, the

request of higher priority level is serviced. If requests of the same priority level are pending at

the end of an instruction, an internal polling sequence determines which request is serviced. The

polling sequence is based on the vector address; an interrupt with a lower vector address has

higher priority than an interrupt with a higher vector address. Note that the polling sequence is

only used to resolve pending requests of the same priority level.

The External Interrupts INT0 and INT1 can each be either level-activated or edge-activated,

depending on bits IT0 and IT1 in Register TCON. The flags that actually generate these inter-

rupts are the IE0 and IE1 bits in TCON. When the service routine is vectored to, hardware clears

the flag that generated an external interrupt only if the interrupt was edge-activated. If the inter-

rupt was level activated, then the external requesting source (rather than the on-chip hardware)

controls the request flag.

The Timer 0 and Timer 1 Interrupts are generated by TF0 and TF1, which are set by a rollover in

their respective Timer/Counter registers (except for Timer 0 in Mode 3). When a timer interrupt is

generated, the on-chip hardware clears the flag that generated it when the service routine is

vectored to.

The Serial Port Interrupt is generated by the logic OR of RI and TI in SCON plus SPIF in SPSR.

None of these flags is cleared by hardware when the service routine is vectored to. In fact, the

service routine normally must determine whether RI, TI, or SPIF generated the interrupt, and the

bit must be cleared by software.

A logic OR of all eight flags in the GPIF register causes the general-purpose interrupt. None of

these flags is cleared by hardware when the service routine is vectored to. The service routine

must determine which bit generated the interrupt, and the bit must be cleared in software. If the

interrupt was level activated, then the external requesting source must de-assert the interrupt

before the flag may be cleared by software.

The CF bit in ACSR generates the Comparator Interrupt. The flag is not cleared by hardware

when the service routine is vectored to and must be cleared by software.

Most of the bits that generate interrupts can be set or cleared by software, with the same result

as though they had been set or cleared by hardware. That is, interrupts can be generated and

pending interrupts can be canceled in software. The two exceptions are the SPI interrupt flag

SPIF and the general-purpose interrupt flags in GPIF. These flags are only set by hardware and

may only be cleared by software.

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