AT89LP216-20PI datasheet(15/90 Pages) ATMEL

15 / 90 page

3621A–MICRO–6/06

AT89LP216 [Preliminary]

10.4

Watchdog Reset

When the Watchdog times out, it will generate an internal reset pulse lasting 16 clock cycles.

Watchdog reset will also set the WDTOVF flag in WDTCON. To prevent a Watchdog reset, the

watchdog reset sequence 1EH/E1H must be written to WDTRST before the Watchdog times

out. See “Programmable Watchdog Timer” on page 57. for details on the operation of the

Watchdog.

10.5

Software Reset

The CPU may generate an internal 16-clock cycle reset pulse by writing the software reset

sequence 5AH/A5H to the WDRST register. A software reset will set the SWRST bit in WDT-

CON. See “Software Reset” on page 58. for more information on software reset.

11. Power Saving Modes

The AT89LP216 supports two different power-reducing modes: Idle and Power-down. These

modes are accessed through the PCON register.

11.1

Idle Mode

Setting the IDL bit in PCON enters idle mode. Idle mode halts the internal CPU clock. The CPU

state is preserved in its entirety, including the RAM, stack pointer, program counter, program

status word, and accumulator. The Port pins hold the logic states they had at the time that Idle

was activated. Idle mode leaves the peripherals running in order to allow them to wake up the

CPU when an interrupt is generated. The timers, UART, SPI, and GPI blocks continue to func-

tion during Idle. The comparator and watchdog may be selectively enabled or disabled during

Idle. Any enabled interrupt source or reset may terminate Idle mode. When exiting Idle mode

with an interrupt, the interrupt will immediately be serviced, and following RETI the next instruc-

tion to be executed will be the one following the instruction that put the device into Idle.

11.2

Power-down Mode

Setting the Power-down (PD) bit in PCON enters Power-down mode. Power-down mode stops

the oscillator and powers down the Flash memory in order to minimize power consumption. Only

the power-on circuitry will continue to draw power during Power-down. During Power-down, the

power supply voltage may be reduced to the RAM keep-alive voltage. The RAM contents will be

retained, but the SFR contents are not guaranteed once V

CC has been reduced. Power-down

may be exited by external reset, power-on reset, or certain interrupts.

11.2.1

Interrupt Recovery from Power-down

Three external interrupts may be configured to terminate Power-down mode. XTAL1 or XTAL2,

when not used for the crystal oscillator or external clock, may be used to exit Power-down

through external interrupts INT0 (P3.2) and INT1 (P3.3). To wake up by external interrupt INT0

or INT1, that interrupt must be enabled and configured for level-sensitive operation. General

purpose interrupt 3 (GPI3) can also wake up the device when the RST pin is disabled. GPI3

must be enabled and configured for low level detection in order to terminate Power-down.

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