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• If the host misses reading result 1 from the FIFO buffer before the second conversion completes, then the

ADC output buffer holds result 2, and the FIFO buffer still holds result 1 [2 | 1].

• Now if the third conversion completes and the host still did not retrieve data from the FIFO buffer, then result

3 overwrites the data in both the ADC output and FIFO buffer [3 | 3].

• In this case, both conversion result 1 and result 2 are lost and cannot be read anymore by the host.

Resulting from the internal structure of the ADC, including the ADC output buffer and the FIFO buffer, the DRDY

pin behaves as described:

• If conversion data are read by the host every time new conversion data become available, then DRDY follows

the format described in the Data Ready (DRDY) section, depending on the DRDY_FMT bit in the MODE

remaining low until either all conversion data are shifted out of the device, or remaining low and going high

briefly before the next time DRDY transitions low. When the DRDY_FMT bit is 1b, new data are indicated by

a short negative pulse on the DRDY pin.

• If the DRDY_FMT bit is 0b and the host does not read conversion data from the FIFO buffer before the next

conversion completes, then DRDY remains low and goes high briefly before the next time DRDY transitions

low (indicating a new conversion).

• If the DRDY_FMT bit is 1b and the host does not read conversion data from the FIFO buffer before the next

conversion completes, then the device skips one DRDY pulse and does not provide another DRDY pulse

until the second following instance when data are ready. Therefore, if the DRDY_FMT bit is 1b and the host

does not read conversion data at all, the DRDY pin toggles at a rate which is half the conversion rate.

8.5.5 Collecting Data for the First Time or After a Pause in Data Collection

Take special precaution when collecting data for the first time or when beginning to collect data again after a

pause. As explained in the ADC Output Buffer and FIFO Buffer section, the device contains a first-in-first-out

(FIFO) buffer in addition to the ADC output buffer. When the host is reading each consecutive sample from

the device, both buffers are updated each time new data are generated, so the DRDY flag in the STATUS

be lost as explained in the ADC Output Buffer and FIFO Buffer section. Either strobe the SYNC/RESET pin

to resynchronize conversions and clear the buffers, or quickly read two data packets when data are read for

the first time or after a gap in reading data. This process ensures predictable DRDY pin behavior. See the

Synchronization section for information about the synchronization feature. These methods do not need to be

employed if each channel data is read for each output data period from when the ADC is enabled.

Figure 8-29 shows an example of how to collect data after a period of the ADC running, but where no data are

being retrieved. In this instance, the SYNC/RESET pin clears the internal buffers and realigns the AMC131M02

output data with the host.

AMC131M02

SBASA56 – SEPTEMBER 2023

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