AMC131M02 datasheet(46/89 Pages) TI

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8.5.3.8 WREG (011a aaaa annn nnnn)

The WREG command allows writing an arbitrary number of contiguous device registers. The binary format of the

command word is 011a aaaa annn nnnn, where a aaaa a is the binary address of the register to begin writing

and nnn nnnn is the unsigned binary number of consecutive registers to write minus one. Send the data to be

written immediately following the command word. Write the intended contents of each register into individual

words, MSB aligned.

If the input CRC is enabled, write this CRC after the register data. The registers are written to the device as

they are shifted into DIN. Therefore, a CRC error does not prevent an erroneous value from being written to a

The device ignores writes to read-only registers or to out-of-bounds addresses. Gaps in the register map

address space are still included in the parameter nnn nnnn, but are not writeable so no change is made to them.

The response to the WREG command that occurs in the following frame appears as 010a aaaa ammm mmmm,

where mmm mmmm is the number of registers actually written minus one. This number can be checked by the

host against nnn nnnn to make sure the expected number of registers are written.

Figure 8-27 shows a typical WREG sequence. In this example, the number of registers to write is larger than

the number of ADC channels and, therefore, the frame is extended beyond the ADC channels and output CRC

word. Make sure all ADC data and output CRC are shifted out during each transaction where new data are

available.

DRDY

SCLK

DIN

DOUT

Channel 0 Data

Channel 1 Data

CRC

Response

Hi-Z

'RQ¶W &DUH

Channel 0 Data

Response

WREG

st UHJLVWHU¶V

data

Command

CRC

nd UHJLVWHU¶V

data

rd UHJLVWHU¶V

data

th UHJLVWHU¶V

data

th UHJLVWHU¶V

data

th UHJLVWHU¶V

data

N-1

th UHJLVWHU¶V

data

th UHJLVWHU¶V

data

CRC

Hi-Z

Figure 8-27. Writing Registers

8.5.4 ADC Output Buffer and FIFO Buffer

As shown in Figure 8-28, the AMC131M02 has two internal data buffers per ADC channel holding conversion

data: an ADC output buffer and a FIFO buffer. Each buffer can only hold one conversion result at a time. The

data output on DOUT is always from the FIFO buffer.

ADC Output

Buffer

ADC Data

ADC

FIFO Buffer

ADC Data

DRDYx

To SPI

Figure 8-28. ADC Data Output Buffer Structure

Whenever an ADC channel generates new conversion data, the ADC output buffer for that channel is updated

immediately with the new data. However, updating the FIFO buffer depends on the previous conversion data

retrieval by the host. There are three scenarios:

• If conversion data (N) stored in the FIFO buffer has already been read by the host at the time that new

conversion data (N+1) become available, then the FIFO buffer is updated with the new conversion data

AMC131M02

SBASA56 – SEPTEMBER 2023

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