WM9705SEFTSLASHV datasheet(25/55 Pages) WOLFSON

25 / 55 page

WM9705

Production Data

PD Rev 4.4 August 2006

AC-LINK AUDIO OUTPUT FRAME (SDATAOUT)

The audio output frame data streams correspond to the multiplexed bundles of all digital output

data targeting the WM9705’s DAC inputs, and control registers. As briefly mentioned earlier, each

audio output frame supports up to 12 20-bit outgoing data time slots. Slot 0 is a special reserved

time slot containing 16-bits, which are used for AC-link protocol infrastructure.

Within slot 0 the first bit is a global bit (SDATAOUT slot 0, bit 15) which flags the validity for the

entire audio frame. If the Valid Frame bit is a 1, this indicates that the current audio frame

contains at least one time slot of valid data. The next 12-bit positions sampled by the WM9705

indicate which of the corresponding 12 time slots contain valid data.

In this way data streams of differing sample rates can be transmitted across AC-link at its fixed

48kHz audio frame rate. Figure 11 illustrates the time slot based AC-link protocol.

SYNC

BITCLK

SDATAOUT

VALID

FRAME

SLOT (1)

SLOT (2)

WM9705 SAMPLES

SYNC ASSERTION HERE

WM9705 SAMPLES

FIRST SDATAOUT

BIT OF FRAME HERE

END OF PREVIOUS AUDIO FRAME

Figure 13 Start of an Audio Output Frame

A new audio output frame begins with a low to high transition of SYNC as shown in Figure 13.

SYNC is synchronous to the rising edge of BITCLK. On the immediately following falling edge of

BITCLK, the WM9705 samples the assertion of SYNC. This falling edge marks the time when

both sides of AC-link are aware of the start of a new audio frame. On the next rising edge of

BITCLK, AC’97 transitions SDATAOUT into the first bit position of slot 0 (Valid Frame bit). Each

new bit position is presented to AC-link on a rising edge of BITCLK, and subsequently sampled by

the WM9705 on the following falling edge of BITCLK. This sequence ensures that data transitions

and subsequent sample points for both incoming and outgoing data streams are time aligned.

Baseline AC’97 specified audio functionality MUST ALWAYS sample rate convert to and from a

fixed 48ks/s on the AC’97 controller. This requirement is necessary to ensure that interoperability

between the AC’97 controller and the WM9705, among other things, can be guaranteed by

definition for baseline specified AC’97 features.

SDATAOUT’s composite stream is MSB justified (MSB first) with all non-valid slot bit positions

stuffed with 0s by the AC’97 controller.

In the event that there are less than 20 valid bits within an assigned and valid time slot, the AC’97

controller always stuffs all trailing non-valid bit positions of the 20-bit slot with 0s.

As an example, consider an 8-bit sample stream that is being played out to one of the WM9705’s

DACs. The first 8 bit positions are presented to the DAC (MSB justified) followed by the next 12

bit positions, which are stuffed with 0s by the AC’97 controller. This ensures that regardless of the

resolution of the implemented DAC (16, 18 or 20-bit), no DC biasing will be introduced by the

least significant bits.

When mono audio sample streams are output from the AC’97 controller, it is necessary that

BOTH left and right sample stream time slots be filled with the same data.

WM9705SEFT/V датащи(PDF) 25 Page - Wolfson Microelectronics plc

WM9705SEFT/V датащи(HTML) 25 Page - Wolfson Microelectronics plc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55

датащи скачать

ссылки URL