WM9705SEFTSLASHV datasheet(24/55 Pages) WOLFSON

24 / 55 page

WM9705

Production Data

PD Rev 4.4 August 2006

SYNC

BITCLK

SDATAOUT

VALID

FRAME

SLOT(1)

SLOT(2)

SLOT(12)

'0'

TAG PHASE

DATA PHASE

20.8

µS (48kHz)

12.288MHz

81.4nS

END OF PREVIOUS

AUDIO FRAME

TIME SLOT 'VALID' BITS

('1' = TIME SLOT CONTAINS

VALID PCM DATA)

SLOT (1)

SLOT (2)

SLOT (3)

SLOT (12)

Figure 12 AC-link Audio Output Frame

The datastreams currently defined by the AC’97 specification include:

PCM playback - 2 output slots

2-channel composite PCM output stream

PCM record data - 2 input slots

2-channel composite PCM input stream

Control - 2 output slots

Control Register write port

Status - 2 input slots

Control Register read port

Optional modem line codec output -

1 output slot

Modem line codec DAC input stream

Optional modem line codec input –

1 input slot

Modem line codec ADC output stream

Optional dedicated microphone input -

1 input slot

Dedicated microphone input stream in

support of stereo AEC and/or other voice

applications.

Synchronisation of all AC-link data transactions is signalled by the WM9705 controller. The

WM9705 drives the serial bit clock onto AC-link, which the AC’97 controller then qualifies with a

synchronisation signal to construct audio frames.

SYNC, fixed at 48kHz, is derived by dividing down the serial clock (BITCLK). BITCLK, fixed at

12.288MHz, provides the necessary clocking granularity to support 12, 20-bit outgoing and

incoming time slots. AC-link serial data is transitioned on each rising edge of BITCLK. The

receiver of AC-link data, (WM9705 for outgoing data and AC’97 controller for incoming data),

samples each serial bit on the falling edges of BITCLK.

The AC-link protocol provides for a special 16-bit time slot (slot 0) wherein each bit conveys a

valid tag for its corresponding time slot within the current audio frame. A 1 in a given bit position

of slot 0 indicates that the corresponding time slot within the current audio frame has been

assigned to a data stream, and contains valid data. If a slot is tagged invalid, it is the

responsibility of the source of the data, (the WM9705 for the input stream, AC’97 controller for the

output stream), to stuff all bit positions with 0s during that slot’s active time.

SYNC remains high for a total duration of 16 BITCLKs at the beginning of each audio frame.

The portion of the audio frame where SYNC is high is defined as the Tag Phase. The remainder

of the audio frame where SYNC is low is defined as the Data Phase. Additionally, for power

savings, all clock, sync, and data signals can be halted. This requires that the WM9705 be

implemented as a static design to allow its Register contents to remain intact when entering a

power savings mode.

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