WM8985GEFLSLASHR datasheet(22/118 Pages) WOLFSON

22 / 118 page

WM8985

Pre-Production

PP, Rev 3.5, March 2007

Figure 9 Typical Power up Sequence where DCVDD is Powered before AVDD1

Figure 9 shows a typical power-up sequence where DCVDD comes up first. First it is assumed that

DCVDD is already up to specified operating voltage. When AVDD1 goes above the minimum

threshold, Vpora, there is enough voltage for the circuit to guarantee PORB is asserted low and the

chip is held in reset. In this condition, all writes to the control interface are ignored. When AVDD1

rises to Vpora_on, PORB is released high and all registers are in their default state and writes to the

control interface may take place.

On power down, where DCVDD falls first, PORB is asserted low whenever DCVDD drops below the

minimum threshold Vpord_off.

SYMBOL

MIN

TYP

MAX

UNIT

Vpora

0.4

0.6

0.8

Vpora_on

0.9

1.2

1.6

Vpora_off

0.4

0.6

0.8

Vpord_on

0.5

0.7

0.9

Vpord_off

0.4

0.6

0.8

Table 2 Typical POR Operation (Typical Simulated Values)

Notes:

If AVDD1 and DCVDD suffer a brown-out (i.e. drop below the minimum recommended operating

level but do not go below Vpora_off or Vpord_off) then the chip will not reset and will resume normal

operation when the voltage is back to the recommended level again.

The chip will enter reset at power down when AVDD1 or DCVDD falls below Vpora_off or Vpord_off.

This may be important if the supply is turned on and off frequently by a power management

system.

The minimum tpor period is maintained even if DCVDD and AVDD1 have zero rise time. This

specification is guaranteed by design rather than test.

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