WM8976 datasheet(93/108 Pages) WOLFSON

93 / 108 page

Pre-Production

WM8976

PP Rev 3.0 April 2006

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

REFER TO

0001

181.6us

1.453ms

10.53ms

0010

363.2us

2.905ms

21.06ms

… (time doubles with every step)

1010

93ms

744ms

5.39s

ALC attack (gain ramp-down) time

(ALCMODE == 0)

Per step

Per 6dB

90% of

range

0000

104us

832us

6ms

0001

208us

1.664ms

12ms

0010

416us

3.328ms

24.1ms

… (time doubles with every step)

0010

1010 or

higher

106ms

852ms

6.18s

ALC attack (gain ramp-down) time

(ALCMODE == 1)

Per step

Per 6dB

90% of

range

0000

22.7us

182.4us

1.31ms

0001

45.4us

363.2us

2.62ms

0010

90.8us

726.4us

5.26ms

… (time doubles with every step)

3:0

ALCATK

0010

1010

23.2ms

186ms

1.348s

Input Limiter/

Automatic

Level Control

(ALC)

8:4

00000

Reserved

NGEN

ALC Noise gate function enable

1 = enable

0 = disable

Input Limiter/

Automatic

Level Control

(ALC)

35 (23h)

2:0

NGTH

000

ALC Noise gate threshold:

000=-39dB

001=-45dB

010=-51db

… (6dB steps)

111=-81dB

Input Limiter/

Automatic

Level Control

(ALC)

8:5

0000

Reserved

PLL

PRESCALE

0 = MCLK input not divided (default)

1 = Divide MCLK by 2 before input to PLL

Master Clock

and Phase

Locked Loop

(PLL)

36 (24h)

3:0

PLLN[3:0]

1000

Integer (N) part of PLL input/output frequency

ratio. Use values greater than 5 and less than 13.

Master Clock

and Phase

Locked Loop

(PLL)

8:6

000

Reserved

37 (25h)

5:0

PLLK[23:18]

01100

Fractional (K) part of PLL1 input/output frequency

ratio (treat as one 24-digit binary number).

Master Clock

and Phase

Locked Loop

(PLL)

38 (26h)

8:0

PLLK[17:9]

01001001

Fractional (K) part of PLL1 input/output frequency

ratio (treat as one 24-digit binary number).

Master Clock

and Phase

Locked Loop

(PLL)

39 (27h)

8:0

PLLK[8:0]

01110100

Fractional (K) part of PLL1 input/output frequency

ratio (treat as one 24-digit binary number).

Master Clock

and Phase

Locked Loop

(PLL)

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