WM8976 datasheet(55/108 Pages) WOLFSON

55 / 108 page

Pre-Production

WM8976

PP Rev 3.0 April 2006

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

R49

Output control

SPKBOOST

0 = speaker gain = -1;

DC = AVDD / 2

1 = speaker gain = +1.5;

DC = 1.5 x AVDD / 2

Power

management

BUFDCOPEN

Dedicated buffer for DC level shifting

output stages when in 1.5x gain

boost configuration.

0=Buffer disabled

1=Buffer enabled (required for 1.5x

gain boost)

Table 41 Speaker Boost Stage Control

SPKBOOST

OUTPUT

STAGE GAIN

OUTPUT DC

LEVEL

OUTPUT STAGE

CONFIGURATION

1x (0dB)

AVDD/2

Inverting

1.5x (3.52dB)

1.5xAVDD/2

Non-inverting

Table 42 Output Boost Stage Details

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

MUTERPGA2INV

Mute input to INVROUT2 mixer

INVROUT2

Invert ROUT2 output

3:1

BEEPVOL

000

AUXR input to ROUT2 inverter gain

000 = -15dB

...

111 = +6dB

R43

Beep control

BEEPEN

0 = mute AUXR beep input

1 = enable AUXR beep input

Table 43 AUXR – ROUT2 BEEP Mixer Function

ZERO CROSS TIMEOUT

A zero-cross timeout function is also provided so that if zero cross is enabled on the input or output

PGAs the gain will automatically update after a timeout period if a zero cross has not occurred. This

is enabled by setting SLOWCLKEN. The timeout period is dependent on the clock input to the digital

and is equal to 2

21 * input clock period.

ADDRESS

BIT

LABEL

DEFAULT

DESCRIPTION

Additional

Control

SLOWCLKEN

Slow clock enable. Used for both the

jack insert detect debounce circuit and

the zero cross timeout.

0 = slow clock disabled

1 = slow clock enabled

Table 44 Timeout Clock Enable Control

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