LT8607 datasheet(18/24 Pages) AD

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LT8609S

Rev. D

For more information www.analog.com

APPLICATIONS INFORMATION

side of the circuit board, and their connections should

be made on that layer. Place a local, unbroken ground

plane under the application circuit on the layer closest

to the surface layer. The SW node should be as small as

possible. Finally, keep the FB and RT nodes small so that

the ground traces will shield them from the SW node.

The exposed pad on the bottom of the package must

be soldered to ground so that the pad is connected to

ground electrically and also acts as a heat sink thermally.

To keep thermal resistance low, extend the ground plane

as much as possible, and add thermal vias under and

near the LT8609S to additional ground planes within

the circuit board and on the bottom side. For mechani-

cal performance during temperature cycles, solder the

corner N/C pins to the ground plane.

PCB Layout

For proper operation and minimum EMI, care must

be taken during printed circuit board layout. Figure 4

shows the recommended component placement with

trace, ground plane and via locations. Note that large,

switched currents flow in the LT8609S’s VIN pins, GND

pins, and the input capacitor (CIN). The loop formed

by the input capacitor should be as small as possible

by placing the capacitor adjacent to the VIN and GND

pins. When using a physically large input capacitor

the resulting loop may become too large in which case

using a small case/value capacitor placed close to the

VIN and GND pins plus a larger capacitor further away

is preferred. These components, along with the induc-

tor and output capacitor, should be placed on the same

Figure 4. PCB Layout

8609S F04

GND VIA

VIN VIA

VOUT VIA

OTHER SIGNAL VIA

COUT

CVCC

CFF

CSS

RPG

CIN

GROUND PLANE ON LAYER 2

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