WM8725

Production Data

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PD Rev 4.1 August 2004

8

The outputs of the 2 DACs are buffered out of the device by buffer amplifiers. These

amplifiers will source load current of several mA and sink current up to 1.5mA, so allowing

significant loads to be driven. The output source is active and the sink is Class A, i.e. fixed

value, so greater loads might be driven if an external ‘pull-down’ resistor is connected at the

output.

Typically an external low pass filter circuit will be used to remove residual sampling noise of

the 64x oversampling used and if desired adjust the signal amplitude and device strength.

SERIAL DATA INTERFACE

WM8725 has serial interface formats that are fully compatible with both normal (MSB first,

right-justified) and I

FORMAT is LOW, normal data format is selected. When the format is HIGH, I

selected. It must be noted that in “packed” mode operation (exactly 32 BCLKs per LRCIN

period), the data word must align exactly with LRCIN clock edges (effectively both left and

right justified at the same time). This is true in both normal and I

FORMAT

DESCRIPTION

0

Normal format

(MSB-first, right justified)

1

I

(Philips serial data protocol)

Table 3 Serial Interface Formats

MSB

MSB

LSB

LSB

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN

Audio Data Word = 16-Bit

1/fs

1

23

14 15 16

1

23

14 15 16

Figure 1 ‘Normal’ Data Input Timing

MSB

MSB

LSB

LSB

LEFT CHANNEL

RIGHT CHANNEL

LRCIN

BCKIN

DIN

Audio Data Word = 16-Bit

1/fs

1

23

14 15 16

1

2

314 15 16

Figure 2 I