PDSP16350

4

SIGNAL

DESCRIPTION

DIN33:0

Data bus for the input register. This input register provides a 34 bit, incremental or absolute, phase

value, if the mode pin is low. Alternatively if the mode pin is high, it provides either an 18 bit phase

increment value, via D17:0, and a 16 bit scale value via D33:18 or a 34 bit phase increment value

depending on the JUMP input see below.

SIN15:0

16 bit sine output data in fractional two’s complement format.

COS15:0

16 bit cosine output data in fractional two’s complement format.

CEN

Clock enable for the data input register. When low, data will be latched on the rising edge of the clock.

When high data will be retained in the input register.

MODE

Mode control input. When low, data in the input register is interpreted as either a 34 bit phase increment

value or a 34 bit absolute phase value. When high, the output multipliers are enabled and will scale the

waveforms with the upper 16 bits in the input register. The phase increment is loaded from the the lower

18 bits. The full 34 bit phase increment register can also be loaded using JUMP see below.

JUMP

With MODE low (Frequency or Phase Modulation)

When low JUMP will allow normal phase incrementing to occur. When high, the data on the input pins

will be interpreted as a 34 bit absolute phase value to replace the present value in the accumulator.

JUMP is internally latched to match the delay through the data input register, and to allow data in the

internal pipeline to be correctly processed. CEN must also be low to latch the required data from DIN.

When Mode is high (Amplitude Modulation)

When low JUMP will allow normal phase incrementing to occur, with the phase increment value taken

from the lower 18 data inputs. When high, the data on the input pins will replace the full 34 bits of the

phase increment register. CEN must also be low to latch the required data.

RES

When high will clear the phase accumulator and phase increment registers, after data in the internal

pipeline has been correctly processed.

CLK

Input clock.

OES

Output enable for SIN 15:0. Outputs are high impedance when OES is high.

OEC

Output enable for COS15:0. Outputs are high impedance when OEC is high.

VIN

Valid input flag. A delayed version of this input is available on the VOUT pin, with the delay matching

the data processing pipeline delay. This input has no other internal function.

VOUT

Valid output flag. See above.

GND

Five ground pins. All must be connected.

VCC

Four +5V pins. All must be connected.

Table 1. Pin Description