M65KA128AL datasheet(12/53 Pages) STMICROELECTRONICS

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Operations

M65KA128AL

12/53

Operations

There are 7 operating modes that control the memory. Each of these is described in this

section, see Table 2: Operating Modes, for a summary.

3.1

Power-Up

The Low Power SDRAM has to be powered up and initialized in a well determined manner:

Power must be applied to VDD and VDDQ simultaneously.

After applying VDD and VDDQ, a minimum pause of 200µs must be respected before

the signals can be toggled.

The Precharge command must then be issued to all banks. The Clock Enable input,

KE, and UDQM/LDQM must be held High until the Precharge command is issued to

make sure that DQ0-DQ15 remain high impedance.

tRP after precharging all the banks, the Mode Register and the Extended Mode

after each register set command.

After configuring the registers, 2 or more Auto Refresh cycles must be executed before

the device is ready for normal operation.

The fourth and fifth steps can be swapped.

3.2

Burst Read

The Read Command is used to switch the device to Burst Read mode (see Section 4.4:

Read command for details). In Burst Read mode the data is output in bursts synchronized

with the clock. A valid Burst Read operation is initiated by driving E and CAS Low, VIL, and

by driving W and RAS High, VIH, at the positive edge of the clock signal, K.

Burst Read can be accompanied by an Auto Precharge cycle depending on the state of the

A10 Address Input. If A10 is High (set to ‘1’) when the Burst Read command is issued, the

Burst Read operation will be followed by an Auto Precharge cycle.

During Burst Read operation, the memory reads data from the activated bank. Different

Burst Types and Lengths can be programmed using the Mode Register bits (see

Section 5.1: Mode Register description). The Burst Types available are Sequential and

Interleaved, selected using Mode Register Bit A3. Possible Burst Lengths are 1-, 2-, 4-, 8-

Word and Full Page, selected using Mode Register Bits A2 to A0.

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