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RECEIVE LOGIC

Receive Parallel Interface

TLK2218

SLLS734 – FEBRUARY 2007

The parallel-to-serial shift register on each channel takes in 10-bit-wide data from either the 8b/10b encoders, if

enabled, or directly from the transmit data bus, and converts it to a serial stream. The shift register is clocked by

the internally generated bit clock, which is 10 times the reference-clock (REFCLK) frequency. The

least-significant bit (LSB) for each channel is transmitted first.

The receiver input data must be ac-coupled and have a rate of 1.0.1.3 Gbps. Resistive termination to match

50-

Ω traces is on-chip. The clock recovery circuitry retimes the input data by extracting a clock from the input

data, and passes on the serial data and this recovered clock to the deserializer. Byte alignment is performed on

K-characters per IEEE 802.3z (see the byte alignment logic section for details).

The receive data bus for all channels is output source centered with the bus clock in the center of the data eye,

allowing direct connection to the protocol device.

In multiplexed channel and nibble interface synchronized channel modes, parallel data to be transferred to the

protocol device is output referenced to both the rising and falling edges of RCLK. RCLK is frequency

synchronous with REFCLK, but has no set phase relationship with respect to REFCLK.

In multiplexed channel mode, channels A and B, C and D, E and F, and G and H are each paired and

interleaved on the same 10-bit bus. Channels B, D, F, H are output referenced to the rising edge of

RCLK/RBCH and falling edge of RBCG (see Figure 6). Channels A, C, E, and G are output referenced to the

falling edge of RCLK/RBCH and rising edge of RBCG. Remaining clocks RBCE–RBCF, RBCC–RBCD, and

RBCA–RBCB are identical copies of RCLK/RBCH–RBCG and could be used as complementary clock pairs.

Figure 6. Multiplexed Channel Receive Timing

In the nibble interface channel mode, channels B, D, F, and H are output on the high-order nibble RDxx[9:5],

while channels A, C, E, G are output on the low-order nibble RDxx[4:0] as shown in Figure 7.

In the nibble interface channel mode, parallel data to be transferred to the protocol device on channel A

(RDBA[4:0]) is output referenced to both the rising and falling edges of RBCA, and channel B (RDBA[9:5]) is

output referenced to both the rising and falling edges of RBCB. Channels C through H are output the same way

with their respective clocks.

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