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TRANSMIT LOGIC

Transmit Clock Interface

Transmit Parallel Interface

TLK2218

SLLS734 – FEBRUARY 2007

The reference clock input must always be in the range of 100 MHz through 130 MHz and is not to be cut in half

while in half rate mode.

The transmit clock must be 1/10 the data rate whether in half rate or full rate mode. That is, the transmit clock

must be in the range of 50 MHz through 65 MHz in half rate mode or 100 MHz through 130 MHz in full rate

mode. The transmit clock and reference clock must come from the same clock source and have NO frequency

deviation between transmit clock and reference clock, with the exception that in half rate mode the transmit clock

is exactly 1/2 the reference clock. The transmit FIFO can accommodate arbitrary phase relationships between

the transmit clock and reference clock, but not for only frequency deviations. In half rate mode, the transmit

FIFO is read by a clock from the TLK2218 PLL which will be exactly half the reference clock frequency, and so

transmit clock must be exactly half the reference clock frequency.

The recovered byte clock is always 1/10 the rate of the data rate, so will be in the range of 50MHz through 65

MHz or will be in the range of 100MHz through 130MHz. If the clock tolerance compensation FIFO's are used,

then the recovered byte clock will be a buffered version of REFCLK in full rate mode or a buffered version of

REFCLK/2 in half rate mode.

MODE0

OPERATING RANGE

High

Half rate 0.5–0.65 Gbps.

Low

Full rate 1.0–1.3 Gbps

The transmit logic converts parallel data into an NRZ serial bit stream with a differential VML output at 1.0–1.3

Gbps, dependent on REFCLK and TCLKx frequency. The input to the transmitter can be either an 8-bit parallel

word plus a control (K) bit, or a 10-bit word.

The TLK2218 provides two transmit clocking modes as summarized in Table 3. In synchronous channel mode,

all input data for all channels is timed from a single input clock, TCLKB. In independent channel mode, four

clocks are used; input data for each pair of channels is timed with one of these clocks.

In synchronous channel mode, data to be transmitted is latched by both the rising and falling edges of TCLKB.

TCLKB must be frequency synchronous with REFCLK (0 ppm), but may have any phase relationship with

respect to REFCLK.

In independent channel mode, input data for channels A and B is referenced from TCLKB. Input data for

channels C and D is referenced from TCLKD. Input data for channels E and F is referenced from TCLKF, and

lastly input data from channels G and H is referenced from TCLKH. TCLKB, TCLKD, TCLKF and TCLKH are

expected to be the same frequency as the reference clock, REFCLK, but of arbitrary phase.

Table 3. Independent vs Synchronous Mode

TCLKSEL (TERMINAL)

TransClkMode MDIO

OPERATING MODE

REGISTER 17.15

Low

Low

Synchronous channel mode

Don't Care

High

Independent channel mode

High

Don't Care

Independent channel mode

The TLK2218 provides source-centered interface to the MAC.

In multiplexed channel mode, channels A and B, C and D, E and F, and G and H are each interleaved on the

same 10-bit bus. Channels B, D, F, H are input referenced to the rising edge of TCLKx. Channels A, C, E, and

G are input referenced to the falling edge of TCLKB (see Figure 4).

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