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FRAME SYNCHRONIZATION

TESTABILITY

IDDQ FUNCTION

LOCAL LOOPBACK

SLK2511B

SLLS763B – JANUARY 2007 – REVISED MARCH 2007

The SLK2511B has a SONET/SDH-compatible frame detection circuit that can be enabled or disabled by the

user. Frame detection is enabled when the FRAMEN pin is high. When enabled it detects the A1, A2 framing

pattern, which is used to locate and align the byte and frame boundaries of the incoming data stream. When

FRAMEN is low the frame detection circuitry is disabled and the byte boundary is frozen to the location found

when detection was previously enabled.

The frame detect circuit searches the incoming data for three consecutive A1 bytes followed immediately by one

A2 byte. The data alignment circuit then aligns the parallel output data to the byte and frame boundaries of the

incoming data stream. During the framing process the parallel data bus does not contain valid and aligned data.

Upon detecting the third A1, A2 framing patterns that are separated by 125

µs from each other, the FSYNC

signal goes high for 4 RXCLK cycles, indicating frame synchronization has been achieved.

The probability that random data in a SONET/SDH data stream mimics the framing pattern in the data payload is

extremely low. However, there is a state machine built in to prevent false reframing if a framing pattern does

show up in the data payload.

The SLK2511B has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed

testing of the transmit/receive portions of the circuitry. The enable pin allows for all circuitry to be disabled so

that an Iddq test can be performed. The PRBS function allows for a BIST (built-in self-test).

When held low, the ENABLE pin disables all quiescent power in both the analog and digital circuitry. This allows

for IDDQ testing on all power supplies and can also be used to conserve power when the link is inactive.

The LLOOP signal pin controls the local loopback. When LLOOP is high, the loopback mode is activated and

the parallel transmit data is selected and presented on the parallel receive data output pins. The parallel transmit

data is also multiplexed and presented on the high-speed serial transmit pins. Local loopback can only be

enabled when the device is under the transceiver mode.

Figure 3. Local Loopback Data Path

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