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SLK2511B

SLLS763B – JANUARY 2007 – REVISED MARCH 2007

Table 1. TERMINAL FUNCTIONS

TERMINAL

TYPE

DESCRIPTION

NAME

NO.

CLOCK PINS

REFCLKP,

94

LVDS/PECL

Differential reference input clock. There is an on-chip 100-

Ω termination resistor differentially

REFCLKN

95

compatible input

placed between REFCLKP and REFCLKN. The dc bias is also provided on-chip for ac-coupled

case.

RXCLKP,

67

LVDS output

Receive data clock. The data on RXDATA(0:3) is on the falling edges of RXCLKP. The interface of

RXCLKN

68

RXDATA(0:3) and RXCLKP is source synchronous (see Figure 7).

TXCLKP,

79

LVDS input

Transmit data clock. The data on TXDATA(0:3) is latched on the rising edge of TXCLKP.

TXCLKN

80

TXCLKSRCP,

70

LVDS output

Transmit clock source. A clock source generated from the SLK2511B to the downstream device

TXCLKSRCN

71

(i.e., framer) that could be used by the downstream device to transmit data back to the SLK2511B.

This clock is frequency-locked to the local reference clock.

SERIAL SIDE DATA PINS

SRXDIP,

14

PECL compatible

Receive differential pairs; high-speed serial inputs.

SRXDIN

15

input

STXDOP,

9

PECL compatible

Transmit differential pairs; high-speed serial outputs.

STXDON

8

input

PARALLEL SIDE DATA PINS

FSYNCP,

73

LVDS output

Frame sync pulse. This signal indicates the frame boundaries of the incoming data stream. If the

FSYNCN

74

frame-detect circuit is enabled, FSYNC pulses for four RXCLKP and RXCLKN clock cycles when it

detects the framing patterns.

RXDATA[0:3]

66–63,

LVDS output

Receive data pins. Parallel data on this bus is valid on the falling edge of RXCLKP (seeFigure 7 ).

P/N

60–57

RXDATA0 is the first bit received in time.

RXPARP,

56

LVDS output

Receive data parity output

RXPARN

55

TXDATA[0:3]

88–81

LVDS input

Transmit data pins. Parallel data on this bus is clocked on the rising edge of TXCLKP. TXDATA0 is

P/N

the first bit transmitted in time.

TXPARP,

99

LVDS input

Transmit data parity input

TXPARN

98

CONTROL/STATUS PINS

AUTO_DETECT

34

TTL input (with

Data rate autodetect enable. Enable the auto-detection function for different data rates. When

pulldown)

AUTO_DETECT is high, the autodetection circuit generates RATEOUT0 and RATEOUT1 to

indicate the data rates for the downstream device.

CONFIG0,

17

TTL input (with

Configuration pins. Put the device under one of the four operation modes: TX only, RX only,

CONFIG1

18

pulldown)

transceiver, or repeater mode. (See Table 4)

ENABLE

44

TTL input (with

Standby enable. When this pin is held low, the device is disabled for IDDQ testing. When high, the

pullup)

device operates normally.

FRAME_EN

27

TTL input (with

Frame sync enable. When this pin is asserted high, the frame synchronization circuit for byte

pullup)

alignment is turned on.

LCKREFN

24

TTL input (with

Lock to reference. When low, RXCLKP/N output is forced to lock to REFCLK. When high,

pullup)

RXCLKP/N is the divided down clock extracted from the receive serial data.

LLOOP

53

TTL input (with

Local loopback enable. When high, the serial output is internally looped back to its serial input.

pulldown)

LOL

45

TTL output

Loss of lock. When the clock recovery loop has locked to the input data stream and the phase

differs by less than 100 ppm from REFCLK then LOL is high. When the phase of the input data

stream differs by more than 100 ppm from REFCLK, then LOL is low. If the difference is too big (>

500 ppm), the LOL output is not valid.

LOOPTIME

51

TTL input (with

Loop timing mode. When high, the PLL for clock synthesizer is bypassed. The recovered clock

pulldown)

timing is used to send the transmit data.

LOS

46

TTL output

Loss of signal. When no transitions appear on the input data stream for more than 2.3

µs, a loss of

signal occurs and LOS goes high. The device also transmits all zeroes downstream using REFCLK

as its clock source. When a valid SONET signal received the LOS signal goes low.

PRBSEN

41

TTL input (with

PRBS testing enable. When this pin is asserted high, the device is put into the PRBS testing mode.

pulldown)

PRE1, PRE2

4 and 5

TTL input (with

Programmable de-emphasis control. Combinations of these two bits can be used to optimize serial

pulldown)

data transmission.

PS

21

TTL input (with

Polarity select. This pin, used with the SIGDET pin, sets the polarity of SIGDET. When high,

pulldown)

SIGDET is an active low signal. When low, SIGDET is an active high signal.

RATEOUT0,

37

TTL output

Autorate detection outputs. When AUTO_DETECT is high, the autodetection circuit generates

RATEOUT1

36

these two bits to indicate the data rates for the downstream device.

RESET

48

TTL input

TXFIFO and LOL reset pin. Low is reset and high is normal operation.

4

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