ADFS7124-4 datasheet(14/93 Pages) AD

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Data Sheet

ADFS7124-4

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

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Rev. 0 | 14 of 93

Figure 9. 32-Lead LFCSP Pin Configuration

Table 6. Pin Function Descriptions

Pin No.

Mnemonic

Description

REGCAPD

Digital LDO Regulator Output. Decouple this pin to DGND with a 0.1 µF capacitor.

IOVDD

Serial Interface Supply Voltage, 1.65 V to 3.6 V. IOVDD is independent of AVDD. Therefore, the serial interface

can operate at 1.65 V with AVDD at 3.6 V, for example.

DGND

Digital Ground Reference Point.

AIN0/IOUT/VBIAS

Analog Input 0/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured through

the configuration registers to be the positive or negative terminal of a differential or pseudodifferential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails

can be generated at this pin.

AIN1/IOUT/VBIAS

Analog Input 1/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured through

the configuration registers to be the positive or negative terminal of a differential or pseudodifferential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails

can be generated at this pin.

6, 7, 10, 11, 14, 15, 18, 19

DNC

Do Not Connect. Do not connect to these pins.

AIN2/IOUT/VBIAS/P1

Analog Input 2/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 1. This input

pin is configured through the configuration registers to be the positive or negative terminal of a differential or

pseudodifferential input. Alternatively, the internal programmable excitation current source can be made available

at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog

power supply rails can be generated at this pin. This pin can also be configured as a general-purpose output bit,

referenced between AVSS and AVDD.

AIN3/IOUT/VBIAS/P2

Analog Input 3/Output of Internal Excitation Current Source/Bias Voltage/General-Purpose Output 2. This input

pin is configured through the configuration registers to be the positive or negative terminal of a differential or

pseudodifferential input. Alternatively, the internal programmable excitation current source can be made available

at this pin. Either IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog

power supply rails can be generated at this pin. This pin can also be configured as a general-purpose output bit,

referenced between AVSS and AVDD.

REFIN1(+)

Positive Reference Input. An external reference can be applied between REFIN1(+) and REFIN1(−). REFIN1(+)

can be anywhere between AVDD and AVSS + 0.5 V. The nominal reference voltage (REFIN1(+) − REFIN1(−)) is

2.5 V, but the device functions with a reference from 0.5 V to AVDD.

REFIN1(−)

Negative Reference Input. This reference input can be anywhere between AVSS and AVDD – 0.5 V.

AIN4/IOUT/VBIAS

Analog Input 4/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured through

the configuration registers to be the positive or negative terminal of a differential or pseudodifferential input.

Alternatively, the internal programmable excitation current source can be made available at this pin. Either

IOUT0 or IOUT1 can be switched to this output. A bias voltage midway between the analog power supply rails

can be generated at this pin.

AIN5/IOUT/VBIAS

Analog Input 5/Output of Internal Excitation Current Source/Bias Voltage. This input pin is configured through

the configuration registers to be the positive or negative terminal of a differential or pseudodifferential input.

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