ADFS7124-4 datasheet(58/93 Pages) AD

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Data Sheet

ADFS7124-4

DIGITAL FILTER

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Rev. 0 | 58 of 93

Figure 89. Sinc3 Filter

Sinc3 Output Data Rate and Settling Time

The output data rate (the rate at which conversions are available on

a single channel when the ADC is continuously converting) equals:

fADC = fCLK/(32 × FS[10:0])

where:

fADC is the output data rate.

fCLK is the controller clock frequency (614.4 kHz in full power mode,

153.6 kHz in mid power mode, and 76.8 kHz in low power mode).

FS[10:0] is the decimal equivalent of the FS[10:0] bits in the filter

The output data rate can be programmed from:

►

9.38 SPS to 19,200 SPS for full power mode

►

2.35 SPS to 4800 SPS for mid power mode

►

1.17 SPS to 2400 SPS for low power mode

The settling time for the sinc3 filter is equal to:

tSETTLE = (3 × 32 × FS[10:0] + Dead time)/fCLK

where, Dead time = 61 when FS[10:0] = 1 and 95 FS[10:0] >1.

Table 57 gives some examples of FS[10:0] settings and the corre-

sponding output data rates and settling times.

Table 57. Examples of Output Data Rates and the Corresponding Settling

Times for the Sinc3 Filter

Power Mode

FS[10:0]

Output Data Rate

(SPS)

Settling Time

(ms)

Full Power (fCLK =

614.4 kHz)

1920

300.15

384

60.15

320

50.15

Mid Power (fCLK =

153.6 kHz)

480

300.61

60.61

50.61

Low Power (fCLK =

76.8 kHz)

240

301.22

61.22

51.22

When a channel change occurs, the modulator and filter are

reset. The complete settling time is allowed to generate the first

conversion after the channel change (see Figure 90). Subsequent

conversions on this channel are available at 1/fADC.

Figure 90. Sinc3 Channel Change

When conversions are performed on a single channel and a step

change occurs, the ADC does not detect the change in the analog

input. Therefore, it continues to output conversions at the program-

med output data rate. However, it is at least three conversions later

before the output data accurately reflects the analog input. If the

step change occurs while the ADC is processing a conversion, the

ADC takes four conversions after the step change to generate a

fully settled result.

Figure 91. Asynchronous Step Change in the Analog Input

Sinc3 Zero Latency

Zero latency is enabled by setting the SINGLE_CYCLE bit in the

filter register to 1. With zero latency, the conversion time when

continuously converting on a single channel approximately equals

the settling time. The benefit of this mode is that a similar period

of time elapses between all conversions irrespective of whether the

conversions occur on one channel or whether several channels are

used.

When the analog input is continuously sampled on a single chan-

nel, the output data rate equals:

fADC = fCLK/(3 × 32 × FS[10:0])

where:

fADC is the output data rate.

fCLK is the controller clock frequency.

FS[10:0] is the decimal equivalent of the FS[10:0] bits in the filter

When switching channels, there is an extra delay in the first conver-

sion of:

Dead time/fCLK

where, Dead time = 61 when FS[10:0] = 1 or 95 when FS > 1.

At low output data rates, this extra delay has little impact on the

value of the settling time. However, at high output data rates, the

delay must be considered. Table 58 summarizes the output data

rate when continuously converting on a single channel and the

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