ES9080 datasheet(29/146 Pages) ESS

29 / 146 page

CONFIDENTIAL ADVANCE INFORMATION 0.4.3

ESS TECHNOLOGY, INC. 109 Bonaventura Drive, San Jose, CA 95134, USA Tel (408) 643-8800 WWW.ESSTECH.COM

ES9080 Product Datasheet

Table 10 provides a list of recommended divider ratios for common input/output frequency combinations when using DATA_CLK as the input source.

The values are shown for 48kHz families. The same dividers can be used for 44.1kHz families to produce the appropriate audio clock.

Fin (MHz)

FBDIV (Nfb)

Fout (MHz)

1.536

0x40000 (128)

49.152

3.072

0x40000 (128)

49.152

6.144

0x40000 (128)

49.152

12.288

0x40000 (128)

49.152

24.576

0x40000 (128)

49.152

Table 10 - Recommended PLL divider ratios for DATA_CLK rates

The APLL also allows for audio clock generation for 44.1kHz families from a 48kHz compatible MCLK source. Table 11 lists divider ratios for

conversion between 48kHz and 44.1kHz families.

Fin (MHz)

FBDIV (Nfb)

Fout (MHz)

49.152

0x528F5 (99.225)

45.1584

24.076

0x528F5 (99.225)

45.1584

0x3CB26 (134.966)

49.152

22.5792

0x3CB26 (134.966)

49.152

Table 11 - Recommended PLL divider ratios for MCLK 48kHz-44.1kHz clock rate conversions

APLL Configuration

Setting up the APLL requires a synchronous I2C register writes to set the divider ratios, input source and analog parameters. The following

sequences are recommended for optimal performance. For more details consult the Register Listings, Reg 192-203

The APLL must be bypassed when using an external clock source through the GPIO1 pin. When using an external clock source these register

settings should be used:

•

Reg 202 = 0x40

•

Reg 192 = 0x03

•

Reg 193 = 0xC3

Configuring the APLL with DATA_CLK input source requires setting the following registers:

•

Reg 202 = 0xC8

•

Reg 192 = 0x01

•

Reg 193 = 0x5F

•

Reg 196 = 0x43

•

Reg 197-199 = FBDIV (feedback divider value)

•

Reg 200[0] = 1’b1

•

Reg 201[1:0], Reg 200[7:1] = Ni (input divider value)

•

Reg 202[2:0], Reg 201[7:2] = No (output divider value)

•

Reg 203 = 0x30

•

Reg 195 = 0xFF

•

Reg 194 = 0x05

Note: Set AUTO_LOCK_EN (Reg 194[2]) & VREF_HOLD_ENABLE (Reg 194[0], once all other PLL registers are set.

IMPORTANT NOTE, when using the PLL, Register 202 (PLL REGISTER7) should be the first register to be configured in both

sequences.

ES9080 датащи(PDF) 29 Page - ESS Technology,Inc

ES9080 датащи(HTML) 29 Page - ESS Technology,Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

датащи скачать

ссылки URL