MP8794

– 16V, 20A, SYNCHRONOUS STEP-DOWN CONVERTER

MP8794 Rev. 1.0

www.MonolithicPower.com

16

12/2/2019

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© 2019 MPS. All Rights Reserved.

If the feedback voltage (VFB) exceeds 116% of

the reference voltage (VREF), OVP is triggered.

The LS-FET remains on until it triggers the low-

side negative current limit (NOCP). Once the

LS-FET triggers NOCP, the LS-FET turns off for

200ns; the HS-FET turns on during this period.

After 200ns, the LS-FET turns on again. The

MP8794 repeats this operation to discharge any

over-voltage on the output. The MP8794 exits

this mode when VFB drops below 105% of VREF.

Over-Temperature Protection (OTP)

The MP8794 has over-temperature protection

(OTP).

The

IC

monitors

the

junction

temperature

internally.

If

the

junction

temperature

exceeds

the

threshold

value

(typically 160°C), the MP8794 latches off the

HS-FET immediately and latches off the LS-

FET once ZC is detected Meanwhile, the SS

capacitor is also discharged. Once the junction

temperature drops to about 130°C, a soft start

is initiated. The OTP function is effective once

the MP8794 is enabled.

Output Voltage Setting and Remote Output

Voltage Sensing

First, choose a value for RFB1. Then RFB2 can be

determined with Equation (4):

REF

FB2

FB1

O

REF

V

R

(k )

R

(k )

VV

 







(4)

To optimize the load transient response, a feed-

forward capacitor (CFF) should be placed in

parallel with RFB1. RFB1 and CFF add an extra

zero frequency to the system, which improves

loop response. RFB1 and CFF are selected so

that the zero frequency formed by RFB1 and CFF

is located at about

20kHz to 60kHz.

Calculate this zero frequency with Equation (5):

Z

FB1

FF

1

f

2

R

C



 



(5)

Power Good (PGOOD)

The MP8794 has a power good output pin

(PGOOD). PGOOD is the open-drain of a

MOSFET. Connect PGOOD to VCC or another

external voltage source below 3.6V through a

pull-up resistor (typically 10

kΩ). After applying

the input voltage, the MOSFET turns on, so

PGOOD is pulled to GND before SS is ready.

After the FB voltage reaches 92.5% of VREF and

a 0.9ms delay , PGOOD is pulled high.

When VFB drops to 80% of VREF or exceeds

116% of the nominal VREF, PGOOD is latched

low. PGOOD can only be pulled high again

after a new SS.

If the input supply fails to power the MP8794,

PGOOD is clamped low, even though PGOOD

is tied to an external DC source through a pull-

up resistor. Figure 5 shows the relationship

between the PGOOD voltage and the pull-up

current.

0

0.2

0.4

0.6

0.8

1

1.2

1.4

1.6

1.8

2

2.2

2.4

2.6

2.8

3

0.6

0.7

0.8

0.9

VPG (V)

Figure 5: PGOOD Clamped Voltage vs. Pull-Up

Current

Enable (EN) Configuration

The MP8794 turns on when EN goes high. The

MP8794 turns off when EN goes low. Do not

leave EN floating. EN can be driven by an

analog or digital control logic signal to enable or

disable the MP8794. The MP8794 provides

accurate EN thresholds, so a resistor divider

from VIN to AGND can be used to program the

input voltage at which the MP8794 is enabled.

This is highly recommended for applications

where there is no dedicated EN control logic

signal. This avoids possible UVLO bouncing

during start-up and shutdown. The resistor

divider values can be determined with Equation

(6):

DOWN

DOWN

UP

EN

START

IN

R

R

R

VIH

V

V







)

(

_

(6)

Where VIHEN is typically 1.22V.